Yield model characterization for analog integrated circuit using pareto-optimal surface

Sawal Hamid Md Ali, Reuben Wilcock, Peter Wilson, Andrew Brown

Research output: Chapter in Book/Report/Conference proceedingConference contribution

6 Citations (Scopus)

Abstract

A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work.

Original languageEnglish
Title of host publicationProceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
Pages1163-1166
Number of pages4
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 - St. Julian's
Duration: 31 Aug 20083 Sep 2008

Other

Other15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008
CitySt. Julian's
Period31/8/083/9/08

Fingerprint

Multiobjective optimization
Transistors
Networks (circuits)
Analog integrated circuits
Costs
Monte Carlo simulation

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Md Ali, S. H., Wilcock, R., Wilson, P., & Brown, A. (2008). Yield model characterization for analog integrated circuit using pareto-optimal surface. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008 (pp. 1163-1166). [4675065] https://doi.org/10.1109/ICECS.2008.4675065

Yield model characterization for analog integrated circuit using pareto-optimal surface. / Md Ali, Sawal Hamid; Wilcock, Reuben; Wilson, Peter; Brown, Andrew.

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 1163-1166 4675065.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Md Ali, SH, Wilcock, R, Wilson, P & Brown, A 2008, Yield model characterization for analog integrated circuit using pareto-optimal surface. in Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008., 4675065, pp. 1163-1166, 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008, St. Julian's, 31/8/08. https://doi.org/10.1109/ICECS.2008.4675065
Md Ali SH, Wilcock R, Wilson P, Brown A. Yield model characterization for analog integrated circuit using pareto-optimal surface. In Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. p. 1163-1166. 4675065 https://doi.org/10.1109/ICECS.2008.4675065
Md Ali, Sawal Hamid ; Wilcock, Reuben ; Wilson, Peter ; Brown, Andrew. / Yield model characterization for analog integrated circuit using pareto-optimal surface. Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2008. 2008. pp. 1163-1166
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