VLSI implementation of inverse discrete wavelet transform for JPEG 2000

M. S. Bhuyan, Nowshad Amin, Md Azrul Hasni Madesa, Md. Shabiul Islam

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper presents hardware design flow of the Inverse Discrete Wavelet Transform (IDWT) core which is the second-most computationally intensive block in JPEG 2000 image compression standard. Lifting Scheme (LS) is implemented in designing the IDWT hardwire module that reduces the number of execution steps involved in computation to almost one-half of those needed with a conventional convolution approach. In addition, the LS is amenable to "in-place" computation, so that the IDWT can be implemented in low memory systems. The IDWT module does not comprise any hardware multiplier unit and therefore suitable for development of high performance image processor. The IDWT module has been developed in VHDL using Quartus II from Altera. The VHDL model is validated through simulation using ModelSim-Altera. Simulation results show the IDWT module can perform three levels inverse transform on a 256x256 forward transformed image in 8.7ms. Latency of the system is calculated 50 ns and the power dissipation by the device is 662 mW. The IDWT module consumes just 57 combinational ALUTs and 60 logic registers of a Stratix II device, and runs at 300 MHz clock frequency, reaches a speed performance suitable for several real-time applications. Throughput in terms of input coefficients processed per second of the IDWT core is 7.13Msamples. The motivation in designing is to reduce its complexity, enhance its performance and to make it suitable development on a reconfigurable FPGA based platform for VLSI implementation.

Original languageEnglish
Title of host publication2007 10th International Conference on Computer and Information Technology, ICCIT
DOIs
Publication statusPublished - 2007
Event2007 10th International Conference on Computer and Information Technology, ICCIT - Dhaka
Duration: 27 Dec 200729 Dec 2007

Other

Other2007 10th International Conference on Computer and Information Technology, ICCIT
CityDhaka
Period27/12/0729/12/07

Fingerprint

Discrete wavelet transforms
Computer hardware description languages
Hardware
Inverse transforms
Image compression
Convolution
Field programmable gate arrays (FPGA)
Clocks
Energy dissipation
Throughput
Data storage equipment

Keywords

  • DWT
  • FPGA
  • Image transforms
  • JPEG 2000

ASJC Scopus subject areas

  • Computer Science Applications
  • Software

Cite this

Bhuyan, M. S., Amin, N., Madesa, M. A. H., & Islam, M. S. (2007). VLSI implementation of inverse discrete wavelet transform for JPEG 2000. In 2007 10th International Conference on Computer and Information Technology, ICCIT [4579438] https://doi.org/10.1109/ICCITECHN.2007.4579438

VLSI implementation of inverse discrete wavelet transform for JPEG 2000. / Bhuyan, M. S.; Amin, Nowshad; Madesa, Md Azrul Hasni; Islam, Md. Shabiul.

2007 10th International Conference on Computer and Information Technology, ICCIT. 2007. 4579438.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Bhuyan, MS, Amin, N, Madesa, MAH & Islam, MS 2007, VLSI implementation of inverse discrete wavelet transform for JPEG 2000. in 2007 10th International Conference on Computer and Information Technology, ICCIT., 4579438, 2007 10th International Conference on Computer and Information Technology, ICCIT, Dhaka, 27/12/07. https://doi.org/10.1109/ICCITECHN.2007.4579438
Bhuyan MS, Amin N, Madesa MAH, Islam MS. VLSI implementation of inverse discrete wavelet transform for JPEG 2000. In 2007 10th International Conference on Computer and Information Technology, ICCIT. 2007. 4579438 https://doi.org/10.1109/ICCITECHN.2007.4579438
Bhuyan, M. S. ; Amin, Nowshad ; Madesa, Md Azrul Hasni ; Islam, Md. Shabiul. / VLSI implementation of inverse discrete wavelet transform for JPEG 2000. 2007 10th International Conference on Computer and Information Technology, ICCIT. 2007.
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