VLSI implementation of 1/2 viterbi decoder for IEEE P802.15-3a UWB communication

Meilana Siswanto, Masuri Othman, Edmond Zahedi

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    This paper presents the design of 1/2 Viterbi decoder for UWB applications following the standard requirements of IEEE P802.15-3a. The main design issues of Viterbi decoder were add-compare-select unit (ACSU), memory management and trace-back methods. In order to meet the requirements of IEEE P802.15-3a UWB, the transition metric unit (TMU) is designed using a finite state machine (FSM) and a parallel carry look-ahead adder (CLA) used to design the addition part of the ACSU. After synthesis using Xilinx synthesis technology (XST), the synthesis report shows that the design has a minimum period of 1.888 ns, equivalent to a data rate of 529.661 Mbps fulfilling more than the standard requirements of IEEE P802.15-3a for UWB, which has a data rate range from 55 to 480 Mbps.

    Original languageEnglish
    Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
    Pages666-670
    Number of pages5
    DOIs
    Publication statusPublished - 2006
    Event2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006 - Kuala Lumpur
    Duration: 29 Nov 20061 Dec 2006

    Other

    Other2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006
    CityKuala Lumpur
    Period29/11/061/12/06

    Fingerprint

    Ultra-wideband (UWB)
    Communication
    Memory management units
    Adders
    Finite automata

    Keywords

    • Convolutional encoder
    • Viterbi algorithm
    • Viterbi decoder
    • VLSI design

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Siswanto, M., Othman, M., & Zahedi, E. (2006). VLSI implementation of 1/2 viterbi decoder for IEEE P802.15-3a UWB communication. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 666-670). [4266700] https://doi.org/10.1109/SMELEC.2006.380717

    VLSI implementation of 1/2 viterbi decoder for IEEE P802.15-3a UWB communication. / Siswanto, Meilana; Othman, Masuri; Zahedi, Edmond.

    IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. p. 666-670 4266700.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Siswanto, M, Othman, M & Zahedi, E 2006, VLSI implementation of 1/2 viterbi decoder for IEEE P802.15-3a UWB communication. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE., 4266700, pp. 666-670, 2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006, Kuala Lumpur, 29/11/06. https://doi.org/10.1109/SMELEC.2006.380717
    Siswanto M, Othman M, Zahedi E. VLSI implementation of 1/2 viterbi decoder for IEEE P802.15-3a UWB communication. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. p. 666-670. 4266700 https://doi.org/10.1109/SMELEC.2006.380717
    Siswanto, Meilana ; Othman, Masuri ; Zahedi, Edmond. / VLSI implementation of 1/2 viterbi decoder for IEEE P802.15-3a UWB communication. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. pp. 666-670
    @inproceedings{8778c76f600b439b819662b365f7ba80,
    title = "VLSI implementation of 1/2 viterbi decoder for IEEE P802.15-3a UWB communication",
    abstract = "This paper presents the design of 1/2 Viterbi decoder for UWB applications following the standard requirements of IEEE P802.15-3a. The main design issues of Viterbi decoder were add-compare-select unit (ACSU), memory management and trace-back methods. In order to meet the requirements of IEEE P802.15-3a UWB, the transition metric unit (TMU) is designed using a finite state machine (FSM) and a parallel carry look-ahead adder (CLA) used to design the addition part of the ACSU. After synthesis using Xilinx synthesis technology (XST), the synthesis report shows that the design has a minimum period of 1.888 ns, equivalent to a data rate of 529.661 Mbps fulfilling more than the standard requirements of IEEE P802.15-3a for UWB, which has a data rate range from 55 to 480 Mbps.",
    keywords = "Convolutional encoder, Viterbi algorithm, Viterbi decoder, VLSI design",
    author = "Meilana Siswanto and Masuri Othman and Edmond Zahedi",
    year = "2006",
    doi = "10.1109/SMELEC.2006.380717",
    language = "English",
    isbn = "0780397312",
    pages = "666--670",
    booktitle = "IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE",

    }

    TY - GEN

    T1 - VLSI implementation of 1/2 viterbi decoder for IEEE P802.15-3a UWB communication

    AU - Siswanto, Meilana

    AU - Othman, Masuri

    AU - Zahedi, Edmond

    PY - 2006

    Y1 - 2006

    N2 - This paper presents the design of 1/2 Viterbi decoder for UWB applications following the standard requirements of IEEE P802.15-3a. The main design issues of Viterbi decoder were add-compare-select unit (ACSU), memory management and trace-back methods. In order to meet the requirements of IEEE P802.15-3a UWB, the transition metric unit (TMU) is designed using a finite state machine (FSM) and a parallel carry look-ahead adder (CLA) used to design the addition part of the ACSU. After synthesis using Xilinx synthesis technology (XST), the synthesis report shows that the design has a minimum period of 1.888 ns, equivalent to a data rate of 529.661 Mbps fulfilling more than the standard requirements of IEEE P802.15-3a for UWB, which has a data rate range from 55 to 480 Mbps.

    AB - This paper presents the design of 1/2 Viterbi decoder for UWB applications following the standard requirements of IEEE P802.15-3a. The main design issues of Viterbi decoder were add-compare-select unit (ACSU), memory management and trace-back methods. In order to meet the requirements of IEEE P802.15-3a UWB, the transition metric unit (TMU) is designed using a finite state machine (FSM) and a parallel carry look-ahead adder (CLA) used to design the addition part of the ACSU. After synthesis using Xilinx synthesis technology (XST), the synthesis report shows that the design has a minimum period of 1.888 ns, equivalent to a data rate of 529.661 Mbps fulfilling more than the standard requirements of IEEE P802.15-3a for UWB, which has a data rate range from 55 to 480 Mbps.

    KW - Convolutional encoder

    KW - Viterbi algorithm

    KW - Viterbi decoder

    KW - VLSI design

    UR - http://www.scopus.com/inward/record.url?scp=35148864081&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=35148864081&partnerID=8YFLogxK

    U2 - 10.1109/SMELEC.2006.380717

    DO - 10.1109/SMELEC.2006.380717

    M3 - Conference contribution

    AN - SCOPUS:35148864081

    SN - 0780397312

    SN - 9780780397316

    SP - 666

    EP - 670

    BT - IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

    ER -