VHDL modeling of built-in-self-test (BIST) for system on chip (SOC) design

Md. Mamun Ibne Reaz, Syed Zahidul Isiarn

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper describes a VHDL modeling environment of built-in-self-test (BIST) for system on chip (SOC) testing to ease the description, verification, simulation and hardware realization. The VHDL model defines a main block, which describe the BIST for SOC through a behavioral and structural description. The three modules test vector generator, circuit under test and response analyzer is connected using its structural description. 8-bit pseudorandom test vector generator is a linear feedback shift register circuit consists of D latches and XOR gates produces 255 different patterns of test vectors for CUT which consists of a 3 to 8 line decoder and a 4 bit adder circuit. In response analyzer, the multiple-input pattern compressor circuit is used to produce signature and a comparator circuit is used for signature analysis. Once detecting the particular approaches for input, output, main block and different modules, the VHDL descriptions are run through a VHDL simulator, which demonstrate the effectiveness of the model.

Original languageEnglish
Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
Pages222-225
Number of pages4
Publication statusPublished - 2002
Externally publishedYes
Event2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002 - Penang
Duration: 19 Dec 200221 Dec 2002

Other

Other2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002
CityPenang
Period19/12/0221/12/02

Fingerprint

Computer hardware description languages
Built-in self test
Networks (circuits)
Comparator circuits
Shift registers
Flip flop circuits
Adders
Compressors
Simulators
Feedback
Hardware
System-on-chip
Testing

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Ibne Reaz, M. M., & Isiarn, S. Z. (2002). VHDL modeling of built-in-self-test (BIST) for system on chip (SOC) design. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 222-225). [1217811]

VHDL modeling of built-in-self-test (BIST) for system on chip (SOC) design. / Ibne Reaz, Md. Mamun; Isiarn, Syed Zahidul.

IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2002. p. 222-225 1217811.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Ibne Reaz, MM & Isiarn, SZ 2002, VHDL modeling of built-in-self-test (BIST) for system on chip (SOC) design. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE., 1217811, pp. 222-225, 2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002, Penang, 19/12/02.
Ibne Reaz MM, Isiarn SZ. VHDL modeling of built-in-self-test (BIST) for system on chip (SOC) design. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2002. p. 222-225. 1217811
Ibne Reaz, Md. Mamun ; Isiarn, Syed Zahidul. / VHDL modeling of built-in-self-test (BIST) for system on chip (SOC) design. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2002. pp. 222-225
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