VHDL environment for pipeline floating point arithmetic logic unit design and simulation

L. F. Rahman, Md. Mamun Ibne Reaz, M. S. Amin

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A pipeline floating point arithmetic logic unit (ALU) design using very high speed hardware description language (VHDL) is introduced. The novelty of the ALU is it gives high performance through the pipelining concept. Pipelining is a technique where multiple instruction executions are overlapped. In the top-down design approach, four arithmetic modules: addition, subtraction, multiplication, and division: are combined to form the floating-point ALU. Each module is divided into smaller modules. Two bits selection determines which operation takes place at a particular time. The pipeline modules are independent of each other. All the modules in the ALU design are realized using VHDL. Design functionalities are validated through simulation and compilation. Test vectors are created to verify the outputs as opposed to the calculated results. Besides verifying the outputs, the outputs' timing diagram and interfacing signals are also tracked to ensure that they adhere to the design specifications. Successful implementation of pipelining in floating point ALU using VHDL fulfills the needs for different high-performance applications.

Original languageEnglish
Pages (from-to)611-619
Number of pages9
JournalJournal of Applied Sciences Research
Volume8
Issue number1
Publication statusPublished - Jan 2012

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Digital arithmetic
Computer hardware description languages
Pipelines
Specifications

Keywords

  • ALU
  • Floating point
  • Microprocessor
  • Pipelining
  • VHDL

ASJC Scopus subject areas

  • General

Cite this

VHDL environment for pipeline floating point arithmetic logic unit design and simulation. / Rahman, L. F.; Ibne Reaz, Md. Mamun; Amin, M. S.

In: Journal of Applied Sciences Research, Vol. 8, No. 1, 01.2012, p. 611-619.

Research output: Contribution to journalArticle

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