Two phase clocked adiabatic static CMOS logic

Nazrul Anuar Nayan, Yasuhiro Takahashi, Toshikazu Sekine

Research output: Chapter in Book/Report/Conference proceedingConference contribution

16 Citations (Scopus)

Abstract

This paper demonstrates the low-energy operation of a two-phase clocked adiabatic static CMOS logic (2PASCL) on the basis of the results obtained in the simulation of a 4-bit ripple- carry adder (RCA) and D-flipflop employing 2PASCL circuit technology. Two-phase unsymmetrical power supply clocks are introduced to increase the logic transition level. Energy dissipation in the unsymmetrical clocked 2PASCL RCA and D-llipllop are 77.2% and 55.5% less than that in a static CMOS at transition frequencies of 10-100 MHz respectively.

Original languageEnglish
Title of host publication2009 International Symposium on System-on-Chip - Proceedings, SoC 2009
Pages83-86
Number of pages4
DOIs
Publication statusPublished - 2009
Externally publishedYes
Event2009 International Symposium on System-on-Chip, SoC 2009 - Tampere
Duration: 5 Oct 20097 Oct 2009

Other

Other2009 International Symposium on System-on-Chip, SoC 2009
CityTampere
Period5/10/097/10/09

Fingerprint

Adders
Clocks
Energy dissipation
Networks (circuits)

ASJC Scopus subject areas

  • Hardware and Architecture
  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Nayan, N. A., Takahashi, Y., & Sekine, T. (2009). Two phase clocked adiabatic static CMOS logic. In 2009 International Symposium on System-on-Chip - Proceedings, SoC 2009 (pp. 83-86). [5335671] https://doi.org/10.1109/SOCC.2009.5335671

Two phase clocked adiabatic static CMOS logic. / Nayan, Nazrul Anuar; Takahashi, Yasuhiro; Sekine, Toshikazu.

2009 International Symposium on System-on-Chip - Proceedings, SoC 2009. 2009. p. 83-86 5335671.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Nayan, NA, Takahashi, Y & Sekine, T 2009, Two phase clocked adiabatic static CMOS logic. in 2009 International Symposium on System-on-Chip - Proceedings, SoC 2009., 5335671, pp. 83-86, 2009 International Symposium on System-on-Chip, SoC 2009, Tampere, 5/10/09. https://doi.org/10.1109/SOCC.2009.5335671
Nayan NA, Takahashi Y, Sekine T. Two phase clocked adiabatic static CMOS logic. In 2009 International Symposium on System-on-Chip - Proceedings, SoC 2009. 2009. p. 83-86. 5335671 https://doi.org/10.1109/SOCC.2009.5335671
Nayan, Nazrul Anuar ; Takahashi, Yasuhiro ; Sekine, Toshikazu. / Two phase clocked adiabatic static CMOS logic. 2009 International Symposium on System-on-Chip - Proceedings, SoC 2009. 2009. pp. 83-86
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