Toward the prediction of irreducible error floor in space time trellis code

Ungku Azmi Iskandar Ungku Chulan, Mardina Abdullah, Nor Fadzilah Abdullah

Research output: Contribution to journalArticle

Abstract

This letter presents a prediction algorithm that foresees the possibility of irreducible error floor for a particular design of a generator matrix G in space time trellis code. This is done without the need of complex and time-consuming simulation, which removes the demand of considerable computational resource. To note, the prediction achieves approximately 93% accuracy and reduces roughly 99% of the temporal cost of simulation. It capitalizes on error prone substructure, a well-known concept from low density parity check code to enable the predictive mechanism. This can be useful in code design where problematic generator matrices can be omitted from consideration.

Original languageEnglish
Article number7811264
Pages (from-to)734-736
Number of pages3
JournalIEEE Communications Letters
Volume21
Issue number4
DOIs
Publication statusPublished - 1 Apr 2017

Fingerprint

Space-time Codes
Trellis codes
Generator
Low-density Parity-check (LDPC) Codes
Prediction
Substructure
Simulation
Resources
Costs
Design

Keywords

  • code design
  • error floor
  • LDPC code
  • STTC

ASJC Scopus subject areas

  • Modelling and Simulation
  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Toward the prediction of irreducible error floor in space time trellis code. / Chulan, Ungku Azmi Iskandar Ungku; Abdullah, Mardina; Abdullah, Nor Fadzilah.

In: IEEE Communications Letters, Vol. 21, No. 4, 7811264, 01.04.2017, p. 734-736.

Research output: Contribution to journalArticle

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