Abstract
This paper presents an approach to design and develop a VLSI system for the simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits. The work involves the design of an interfacing unit on PCB containing interfacing circuits for parallel data exchange between a test processor and a microcomputer. This allows IDDQ measurement for every vector used for logic testing, performing logic testing simultaneously, providing a promising IDDQ fault coverage and reducing substantially the time and cost of testing. Three basic test development strategies are considered. They are functional test development, structural test development and physical defect test development. Mixed-mode testing facility is adopted to enhance the performance and reduce the testing time.
Original language | English |
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Title of host publication | 2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 234-235 |
Number of pages | 2 |
ISBN (Print) | 0780381394, 9780780381391 |
DOIs | |
Publication status | Published - 2003 |
Externally published | Yes |
Event | International Semiconductor Device Research Symposium, ISDRS 2003 - Washington, United States Duration: 10 Dec 2003 → 12 Dec 2003 |
Other
Other | International Semiconductor Device Research Symposium, ISDRS 2003 |
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Country | United States |
City | Washington |
Period | 10/12/03 → 12/12/03 |
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ASJC Scopus subject areas
- Electrical and Electronic Engineering
Cite this
The simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits. / Ibne Reaz, Md. Mamun; Yasin, Faisal Mohd; Sulaiman, Mohd Shahiman; Ali, Mohd Alauddin.
2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2003. p. 234-235 1272076.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - The simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits
AU - Ibne Reaz, Md. Mamun
AU - Yasin, Faisal Mohd
AU - Sulaiman, Mohd Shahiman
AU - Ali, Mohd Alauddin
PY - 2003
Y1 - 2003
N2 - This paper presents an approach to design and develop a VLSI system for the simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits. The work involves the design of an interfacing unit on PCB containing interfacing circuits for parallel data exchange between a test processor and a microcomputer. This allows IDDQ measurement for every vector used for logic testing, performing logic testing simultaneously, providing a promising IDDQ fault coverage and reducing substantially the time and cost of testing. Three basic test development strategies are considered. They are functional test development, structural test development and physical defect test development. Mixed-mode testing facility is adopted to enhance the performance and reduce the testing time.
AB - This paper presents an approach to design and develop a VLSI system for the simultaneous logic and IDDQ testing of CMOS ICs with mixed-mode testing facility for sequential circuits. The work involves the design of an interfacing unit on PCB containing interfacing circuits for parallel data exchange between a test processor and a microcomputer. This allows IDDQ measurement for every vector used for logic testing, performing logic testing simultaneously, providing a promising IDDQ fault coverage and reducing substantially the time and cost of testing. Three basic test development strategies are considered. They are functional test development, structural test development and physical defect test development. Mixed-mode testing facility is adopted to enhance the performance and reduce the testing time.
UR - http://www.scopus.com/inward/record.url?scp=84945263708&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84945263708&partnerID=8YFLogxK
U2 - 10.1109/ISDRS.2003.1272076
DO - 10.1109/ISDRS.2003.1272076
M3 - Conference contribution
AN - SCOPUS:84945263708
SN - 0780381394
SN - 9780780381391
SP - 234
EP - 235
BT - 2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings
PB - Institute of Electrical and Electronics Engineers Inc.
ER -