Test processor ASIC design

Md Liakot Ali, Zahari Mohamed Darus, Mohd Alauddin, Mohd Ali, Iftekhar Ahmed

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    3 Citations (Scopus)

    Abstract

    In this paper, a design of a Test Processor ASIC employing probabilistic approach is presented. The test processor chip is computer programmable. It consists of linear feedback shift register (LFSR) which can select one of 16 polynomials and set user programmable seed for every test set, signature analyzer and 3 built-in RAMs and other control circuitry. It is capable of generating random numbers and apply them to the circuit under test (CUT) and then retrieve the responses from the CUT. It can generate signature by compressing the response data and detect circuit faults by comparing this signature with that of a good CUT. This ASIC can be used to design low cost IC tester of reliable performance.

    Original languageEnglish
    Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
    Place of PublicationPiscataway, NJ, United States
    PublisherIEEE
    Pages261-265
    Number of pages5
    Publication statusPublished - 1997
    EventProceedings of the 1996 IEEE International Conference on Semiconductor Electronics, ICSE - Penang, Malaysia
    Duration: 26 Nov 199628 Nov 1996

    Other

    OtherProceedings of the 1996 IEEE International Conference on Semiconductor Electronics, ICSE
    CityPenang, Malaysia
    Period26/11/9628/11/96

    Fingerprint

    Application specific integrated circuits
    Networks (circuits)
    Shift registers
    Random access storage
    Seed
    Polynomials
    Feedback
    Costs

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Ali, M. L., Darus, Z. M., Alauddin, M., Ali, M., & Ahmed, I. (1997). Test processor ASIC design. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 261-265). Piscataway, NJ, United States: IEEE.

    Test processor ASIC design. / Ali, Md Liakot; Darus, Zahari Mohamed; Alauddin, Mohd; Ali, Mohd; Ahmed, Iftekhar.

    IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. Piscataway, NJ, United States : IEEE, 1997. p. 261-265.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Ali, ML, Darus, ZM, Alauddin, M, Ali, M & Ahmed, I 1997, Test processor ASIC design. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. IEEE, Piscataway, NJ, United States, pp. 261-265, Proceedings of the 1996 IEEE International Conference on Semiconductor Electronics, ICSE, Penang, Malaysia, 26/11/96.
    Ali ML, Darus ZM, Alauddin M, Ali M, Ahmed I. Test processor ASIC design. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. Piscataway, NJ, United States: IEEE. 1997. p. 261-265
    Ali, Md Liakot ; Darus, Zahari Mohamed ; Alauddin, Mohd ; Ali, Mohd ; Ahmed, Iftekhar. / Test processor ASIC design. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. Piscataway, NJ, United States : IEEE, 1997. pp. 261-265
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