Study of the side gate junctionless transistor in accumulation region

Arash Dehzangi, Farhad Larki, Sawal Hamid Md Ali, Sabar Derita Hutagalung, Md. Shabiul Islam, Azman Jalar @ Jalil

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Purpose-The purpose of this paper is to analyse the operation of p-type side gate junctionless silicon transistor (SGJLT) in accumulation region through experimental measurements and 3-D TCAD simulation results. The variation of electric field components, carrier's concentration and valence band edge energy towards the accumulation region is explored with the aim of finding the origin of SGJLT performance in the accumulation operational condition. Design/methodology/approach-The device is fabricated by atomic force microscopy nanolithography on silicon-on-insulator wafer. The output and transfer characteristics of the device are obtained using 3-D Technology Computer Aided Design (TCAD) Sentaurus software and compared with experimental measurement results. The advantages of AFM nanolithography in contact mode and Silicon on Insulator (SOI) technology were implemented to fabricate a simple structure which exhibits the behaviour of field effect transistors. The device has 200-nm channel length, 100-nm gate gap and 4 m for the distance between the source and drain contacts. The characteristics of the fabricated device were measured using an Agilent HP4156C semiconductor parameter analyzer (SPA). A 3-D TCAD Sentaurus tool is used as the simulation platform. The Boltzmann statistics is adopted because of the low doping concentration of the channel. Hydrodynamic model is taken to be as the main transport model for all simulations, and the quantum mechanical effects are ignored. A doping dependent Masetti mobility model was also included as well as an electric field dependent model with Shockley-Read-Hall (SRH) carrier recombination/generation. Findings-We have obtained that the device is a normally on state device mainly because of the lack of work functional difference between the gate and the channel. Analysis of electric field components' variation, carrier's concentration and valence band edge energy reveals that increasing the negative gate voltage drives the device into accumulation region; however, it is unable to increase the drain current significantly. The positive slope of the hole quasi-Fermi level in the accumulation region presents mechanism of carriers' movement from source to drain. The influence of electric field because of drain and gate voltage on charge distribution explains a low increasing of the drain current when the device operates in accumulation regime. Originality/value-The proposed side gate junctionless transistors simplify the fabrication process, because of the lack of gate oxide and physical junctions, and implement the atomic force microscopy nanolithography for fabrication process. The optimized structure with lower gap between gate and channel and narrower channel would present the output characteristics near the ideal transistors for next generation of scaled-down devices in both accumulation and depletion region. The presented findings are verified through experimental measurements and simulation results.

Original languageEnglish
Pages (from-to)61-67
Number of pages7
JournalMicroelectronics International
Volume33
Issue number2
DOIs
Publication statusPublished - 2016

Fingerprint

Nanolithography
Transistors
Silicon
transistors
Electric fields
Computer aided design
Drain current
Valence bands
Carrier concentration
Atomic force microscopy
Doping (additives)
Silicon on insulator technology
computer aided design
Fabrication
silicon transistors
Charge distribution
Electric potential
electric fields
Field effect transistors
Fermi level

Keywords

  • Semiconductor technology
  • Thick/thin film technology

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials
  • Surfaces, Coatings and Films
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics

Cite this

Study of the side gate junctionless transistor in accumulation region. / Dehzangi, Arash; Larki, Farhad; Md Ali, Sawal Hamid; Hutagalung, Sabar Derita; Islam, Md. Shabiul; Jalar @ Jalil, Azman.

In: Microelectronics International, Vol. 33, No. 2, 2016, p. 61-67.

Research output: Contribution to journalArticle

Dehzangi, Arash ; Larki, Farhad ; Md Ali, Sawal Hamid ; Hutagalung, Sabar Derita ; Islam, Md. Shabiul ; Jalar @ Jalil, Azman. / Study of the side gate junctionless transistor in accumulation region. In: Microelectronics International. 2016 ; Vol. 33, No. 2. pp. 61-67.
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