Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method

A. H Afifah Maheran, P. Susthitha Menon N V Visvanathan, S. Shaari, I. Ahmad, Z. A Noor Faizah

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper aims to study the effect of process parameter variation on a nano-scaled planar p-type MOSFET (metal-oxide-semiconductor field-effect transistor) device for 22 nm technology using Taguchi's L9 orthogonal array. The device was constructed with high-k/metal gate consisting of Titanium dioxide (TiO2) and Tungsten silicide (WSix) metal gate using an industrial-based numerical simulator. Using Taguchi's Signal-to-noise ratio (SNR) of nominal-the-best (NTB), the compensation implantation has been as identified as the dominant factor influencing the Vth value with 67.77% while the Halo implantation tilting angle has been identified as the adjustment factor. Upon optimization, the Vth value is-0.29538 V which is within the requirements of the International Technology Roadmap for Semiconductors (ITRS) 2012 which is-0.289 V ± 12.7 %.

Original languageEnglish
Title of host publicationRSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Print)9781479985500
DOIs
Publication statusPublished - 11 Dec 2015
Event10th IEEE Regional Symposium on Micro and Nano Electronics, RSM 2015 - Kuala Terengganu, Malaysia
Duration: 19 Aug 201521 Aug 2015

Other

Other10th IEEE Regional Symposium on Micro and Nano Electronics, RSM 2015
CountryMalaysia
CityKuala Terengganu
Period19/8/1521/8/15

Fingerprint

Taguchi methods
p-type semiconductors
MOSFET devices
Threshold voltage
metal oxide semiconductors
threshold voltage
implantation
field effect transistors
Metals
Tungsten
optimization
titanium oxides
metals
Titanium dioxide
simulators
halos
Signal to noise ratio
tungsten
signal to noise ratios
Simulators

Keywords

  • 22 nm
  • high-k/metal gate
  • PMOS
  • Taguchi Method
  • threshold voltage
  • TiO/WSix

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Instrumentation
  • Electrical and Electronic Engineering

Cite this

Maheran, A. H. A., N V Visvanathan, P. S. M., Shaari, S., Ahmad, I., & Faizah, Z. A. N. (2015). Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method. In RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings [7354989] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/RSM.2015.7354989

Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method. / Maheran, A. H Afifah; N V Visvanathan, P. Susthitha Menon; Shaari, S.; Ahmad, I.; Faizah, Z. A Noor.

RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. 7354989.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Maheran, AHA, N V Visvanathan, PSM, Shaari, S, Ahmad, I & Faizah, ZAN 2015, Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method. in RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings., 7354989, Institute of Electrical and Electronics Engineers Inc., 10th IEEE Regional Symposium on Micro and Nano Electronics, RSM 2015, Kuala Terengganu, Malaysia, 19/8/15. https://doi.org/10.1109/RSM.2015.7354989
Maheran AHA, N V Visvanathan PSM, Shaari S, Ahmad I, Faizah ZAN. Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method. In RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc. 2015. 7354989 https://doi.org/10.1109/RSM.2015.7354989
Maheran, A. H Afifah ; N V Visvanathan, P. Susthitha Menon ; Shaari, S. ; Ahmad, I. ; Faizah, Z. A Noor. / Statistical optimization of process parameters for threshold voltage in 22 nm p-Type MOSFET using Taguchi method. RSM 2015 - 2015 IEEE Regional Symposium on Micro and Nano Electronics, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015.
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abstract = "This paper aims to study the effect of process parameter variation on a nano-scaled planar p-type MOSFET (metal-oxide-semiconductor field-effect transistor) device for 22 nm technology using Taguchi's L9 orthogonal array. The device was constructed with high-k/metal gate consisting of Titanium dioxide (TiO2) and Tungsten silicide (WSix) metal gate using an industrial-based numerical simulator. Using Taguchi's Signal-to-noise ratio (SNR) of nominal-the-best (NTB), the compensation implantation has been as identified as the dominant factor influencing the Vth value with 67.77{\%} while the Halo implantation tilting angle has been identified as the adjustment factor. Upon optimization, the Vth value is-0.29538 V which is within the requirements of the International Technology Roadmap for Semiconductors (ITRS) 2012 which is-0.289 V ± 12.7 {\%}.",
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AU - Ahmad, I.

AU - Faizah, Z. A Noor

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N2 - This paper aims to study the effect of process parameter variation on a nano-scaled planar p-type MOSFET (metal-oxide-semiconductor field-effect transistor) device for 22 nm technology using Taguchi's L9 orthogonal array. The device was constructed with high-k/metal gate consisting of Titanium dioxide (TiO2) and Tungsten silicide (WSix) metal gate using an industrial-based numerical simulator. Using Taguchi's Signal-to-noise ratio (SNR) of nominal-the-best (NTB), the compensation implantation has been as identified as the dominant factor influencing the Vth value with 67.77% while the Halo implantation tilting angle has been identified as the adjustment factor. Upon optimization, the Vth value is-0.29538 V which is within the requirements of the International Technology Roadmap for Semiconductors (ITRS) 2012 which is-0.289 V ± 12.7 %.

AB - This paper aims to study the effect of process parameter variation on a nano-scaled planar p-type MOSFET (metal-oxide-semiconductor field-effect transistor) device for 22 nm technology using Taguchi's L9 orthogonal array. The device was constructed with high-k/metal gate consisting of Titanium dioxide (TiO2) and Tungsten silicide (WSix) metal gate using an industrial-based numerical simulator. Using Taguchi's Signal-to-noise ratio (SNR) of nominal-the-best (NTB), the compensation implantation has been as identified as the dominant factor influencing the Vth value with 67.77% while the Halo implantation tilting angle has been identified as the adjustment factor. Upon optimization, the Vth value is-0.29538 V which is within the requirements of the International Technology Roadmap for Semiconductors (ITRS) 2012 which is-0.289 V ± 12.7 %.

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