Source-Coupled Logic (SCL)

Operation and delay analysis

Mohamed Azaga, Masuri Othman

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    This work describe and present the analysis for the Source-Coupled Logic (SCL) inverter. The SCL inverter circuit model and its operation is defined. The analysis for the SCL is carried from the point of view of input/output voltage characteristics, and the effect of noise margin. Finally, the inverter gate delay model is described, and the effect of biasing current on the delay is shown. All simulation is done based on the 0.18μ Silterra process, and using Cadence Spectre simulation platform. The result shows that, the delay of the SCL inverter is decreased as biasing current increase.

    Original languageEnglish
    Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
    Pages392-396
    Number of pages5
    DOIs
    Publication statusPublished - 2006
    Event2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006 - Kuala Lumpur
    Duration: 29 Nov 20061 Dec 2006

    Other

    Other2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006
    CityKuala Lumpur
    Period29/11/061/12/06

    Fingerprint

    Coupled circuits
    Logic circuits
    Electric potential

    ASJC Scopus subject areas

    • Engineering(all)

    Cite this

    Azaga, M., & Othman, M. (2006). Source-Coupled Logic (SCL): Operation and delay analysis. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 392-396). [4266638] https://doi.org/10.1109/SMELEC.2006.381088

    Source-Coupled Logic (SCL) : Operation and delay analysis. / Azaga, Mohamed; Othman, Masuri.

    IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. p. 392-396 4266638.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Azaga, M & Othman, M 2006, Source-Coupled Logic (SCL): Operation and delay analysis. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE., 4266638, pp. 392-396, 2006 IEEE International Conference on Semiconductor Electronics, ICSE 2006, Kuala Lumpur, 29/11/06. https://doi.org/10.1109/SMELEC.2006.381088
    Azaga M, Othman M. Source-Coupled Logic (SCL): Operation and delay analysis. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. p. 392-396. 4266638 https://doi.org/10.1109/SMELEC.2006.381088
    Azaga, Mohamed ; Othman, Masuri. / Source-Coupled Logic (SCL) : Operation and delay analysis. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2006. pp. 392-396
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