Single core hardware module to implement partial encryption of compressed image

Md. Mamun Ibne Reaz, Md Syedul Amin, Fazida Hanim Hashim, Khandaker Asaduzzaman

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Problem statement: Real-time secure image and video communication is challenging due to the processing time and computational requirement for encryption and decryption. In order to cope with these concerns, innovative image compression and encryption techniques are required. Approach: In this research, we have introduced partial encryption technique on compressed images and implemented the algorithm on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The compression algorithm decomposes images into several different parts. We have used a secured encryption algorithm to encrypt only the crucial parts, which are considerably smaller than the original image, which result in significant reduction in processing time and computational requirement for encryption and decryption. The breadth-first traversal linear lossless quadtree decomposition method is used for the partial compression and RSA is used for the encryption. Results: Functional simulations were commenced to verify the functionality of the individual modules and the system on four different images. We have validated the advantage of the proposed approach through comparison, verification and analysis. The design has utilized 2928 units of LC with a system frequency of 13.42MHz. Conclusion: In this research, the FPGA prototyping of a partial encryption of compressed images using lossless quadtree compression and RSA encryption has been successfully implemented with minimum logic cells. It is found that the compression process is faster than the decompression process in linear quadtree approach. Moreover, the RSA simulations show that the encryption process is faster than the decryption process for all four images tested.

Original languageEnglish
Pages (from-to)566-573
Number of pages8
JournalAmerican Journal of Applied Sciences
Volume8
Issue number6
Publication statusPublished - 2011

Fingerprint

Computer hardware
Cryptography
Field programmable gate arrays (FPGA)
Processing
Image compression
Decomposition
Hardware
Communication

Keywords

  • Data Encryption Standard (DES)
  • Encryption algorithm
  • Encryption techniques
  • Field- Programmable Gate Arrays (FPGA)
  • Partial encryption
  • Quadtree compression
  • Real-time secure image
  • Video communication

ASJC Scopus subject areas

  • General

Cite this

Single core hardware module to implement partial encryption of compressed image. / Ibne Reaz, Md. Mamun; Amin, Md Syedul; Hashim, Fazida Hanim; Asaduzzaman, Khandaker.

In: American Journal of Applied Sciences, Vol. 8, No. 6, 2011, p. 566-573.

Research output: Contribution to journalArticle

@article{8791a6fd54f843819408acd99634ea77,
title = "Single core hardware module to implement partial encryption of compressed image",
abstract = "Problem statement: Real-time secure image and video communication is challenging due to the processing time and computational requirement for encryption and decryption. In order to cope with these concerns, innovative image compression and encryption techniques are required. Approach: In this research, we have introduced partial encryption technique on compressed images and implemented the algorithm on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The compression algorithm decomposes images into several different parts. We have used a secured encryption algorithm to encrypt only the crucial parts, which are considerably smaller than the original image, which result in significant reduction in processing time and computational requirement for encryption and decryption. The breadth-first traversal linear lossless quadtree decomposition method is used for the partial compression and RSA is used for the encryption. Results: Functional simulations were commenced to verify the functionality of the individual modules and the system on four different images. We have validated the advantage of the proposed approach through comparison, verification and analysis. The design has utilized 2928 units of LC with a system frequency of 13.42MHz. Conclusion: In this research, the FPGA prototyping of a partial encryption of compressed images using lossless quadtree compression and RSA encryption has been successfully implemented with minimum logic cells. It is found that the compression process is faster than the decompression process in linear quadtree approach. Moreover, the RSA simulations show that the encryption process is faster than the decryption process for all four images tested.",
keywords = "Data Encryption Standard (DES), Encryption algorithm, Encryption techniques, Field- Programmable Gate Arrays (FPGA), Partial encryption, Quadtree compression, Real-time secure image, Video communication",
author = "{Ibne Reaz}, {Md. Mamun} and Amin, {Md Syedul} and Hashim, {Fazida Hanim} and Khandaker Asaduzzaman",
year = "2011",
language = "English",
volume = "8",
pages = "566--573",
journal = "American Journal of Applied Sciences",
issn = "1546-9239",
publisher = "Science Publications",
number = "6",

}

TY - JOUR

T1 - Single core hardware module to implement partial encryption of compressed image

AU - Ibne Reaz, Md. Mamun

AU - Amin, Md Syedul

AU - Hashim, Fazida Hanim

AU - Asaduzzaman, Khandaker

PY - 2011

Y1 - 2011

N2 - Problem statement: Real-time secure image and video communication is challenging due to the processing time and computational requirement for encryption and decryption. In order to cope with these concerns, innovative image compression and encryption techniques are required. Approach: In this research, we have introduced partial encryption technique on compressed images and implemented the algorithm on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The compression algorithm decomposes images into several different parts. We have used a secured encryption algorithm to encrypt only the crucial parts, which are considerably smaller than the original image, which result in significant reduction in processing time and computational requirement for encryption and decryption. The breadth-first traversal linear lossless quadtree decomposition method is used for the partial compression and RSA is used for the encryption. Results: Functional simulations were commenced to verify the functionality of the individual modules and the system on four different images. We have validated the advantage of the proposed approach through comparison, verification and analysis. The design has utilized 2928 units of LC with a system frequency of 13.42MHz. Conclusion: In this research, the FPGA prototyping of a partial encryption of compressed images using lossless quadtree compression and RSA encryption has been successfully implemented with minimum logic cells. It is found that the compression process is faster than the decompression process in linear quadtree approach. Moreover, the RSA simulations show that the encryption process is faster than the decryption process for all four images tested.

AB - Problem statement: Real-time secure image and video communication is challenging due to the processing time and computational requirement for encryption and decryption. In order to cope with these concerns, innovative image compression and encryption techniques are required. Approach: In this research, we have introduced partial encryption technique on compressed images and implemented the algorithm on Altera FLEX10K FPGA device that allows for efficient hardware implementation. The compression algorithm decomposes images into several different parts. We have used a secured encryption algorithm to encrypt only the crucial parts, which are considerably smaller than the original image, which result in significant reduction in processing time and computational requirement for encryption and decryption. The breadth-first traversal linear lossless quadtree decomposition method is used for the partial compression and RSA is used for the encryption. Results: Functional simulations were commenced to verify the functionality of the individual modules and the system on four different images. We have validated the advantage of the proposed approach through comparison, verification and analysis. The design has utilized 2928 units of LC with a system frequency of 13.42MHz. Conclusion: In this research, the FPGA prototyping of a partial encryption of compressed images using lossless quadtree compression and RSA encryption has been successfully implemented with minimum logic cells. It is found that the compression process is faster than the decompression process in linear quadtree approach. Moreover, the RSA simulations show that the encryption process is faster than the decryption process for all four images tested.

KW - Data Encryption Standard (DES)

KW - Encryption algorithm

KW - Encryption techniques

KW - Field- Programmable Gate Arrays (FPGA)

KW - Partial encryption

KW - Quadtree compression

KW - Real-time secure image

KW - Video communication

UR - http://www.scopus.com/inward/record.url?scp=79959419892&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79959419892&partnerID=8YFLogxK

M3 - Article

VL - 8

SP - 566

EP - 573

JO - American Journal of Applied Sciences

JF - American Journal of Applied Sciences

SN - 1546-9239

IS - 6

ER -