Single core hardware modeling of built-in-self-test for system on chip design

Md. Mamun Ibne Reaz, M. S. Amin, J. Jalil

Research output: Contribution to journalArticle

Abstract

This study describes a hardware modeling environment of built-in-self-test (BIST) for System on Chip (SOC) testing to ease the description, verification, simulation and hardware realization on Altera FLEX10K FPGA device. The very high speed hardware description language (VHDL) model defines a main block, which describe the BIST for SOC through a behavioral and structural description. The three modules test vector generator, circuit under test and response analyzer is connected using its structural description. 8-bit pseudorandom test vector generator is a linear feedback shift register circuit consists of D latches and XOR gates produces 255 different patterns of test vectors for CUT which consists of a 3 to 8 line decoder and a 4 bit adder circuit. In response analyzer, the multiple-input pattern compressor circuit is used to produce signature and a comparator circuit is used for signature analysis. The design is modularized and each module is modeled individually using hardware description language VHDL. This is followed by the timing analysis and circuit synthesis for the validation, functionality and performance of the designated circuit, which supports the practicality, advantages and effectiveness of the proposed hardware realization for the applications with a maximum clock frequency of 31.4 MHz.

Original languageEnglish
Pages (from-to)819-824
Number of pages6
JournalResearch Journal of Applied Sciences, Engineering and Technology
Volume4
Issue number7
Publication statusPublished - 2012

Fingerprint

Built-in self test
Hardware
Computer hardware description languages
Networks (circuits)
Comparator circuits
Shift registers
Flip flop circuits
Adders
Compressors
System-on-chip
Field programmable gate arrays (FPGA)
Clocks
Feedback
Testing

Keywords

  • Built-in-self-test
  • Circuit under test
  • Design for testability
  • Latches
  • System on chip
  • VHDL

ASJC Scopus subject areas

  • Engineering(all)
  • Computer Science(all)

Cite this

Single core hardware modeling of built-in-self-test for system on chip design. / Ibne Reaz, Md. Mamun; Amin, M. S.; Jalil, J.

In: Research Journal of Applied Sciences, Engineering and Technology, Vol. 4, No. 7, 2012, p. 819-824.

Research output: Contribution to journalArticle

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