Scaling down of the 32 nm to 22 nm gate length NMOS transistor

A. H. Afifah Maheran, P. Susthitha Menon N V Visvanathan, I. Ahmad, H. A. Elgomati, Burhanuddin Yeop Majlis, F. Salehuddin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

10 Citations (Scopus)

Abstract

In this paper, we provide the downscaling design and simulation of NMOS transistor with 22 nm gate length, based on the 32 nm design simulation from our previous research. A combination Titanium dioxide (TiO2) was used as the high-k material and tungsten silicide (WSix) was used as the metal gate instead of SiO2 dielectric from the 32 nm gate length device. The NMOS transistor was simulated using fabrication tool ATHENA and electrical characterization was simulated using ATLAS. The scale down ratio was used and the dimension of device was scaled down with minimal issues. Our simulation shows that the optimal value of threshold voltage (Vth) and leakage currents (Ion and Ioff) was achieved according to specification in ITRS 2011. This provides a benchmark towards the fabrication of 22 nm NMOS in future work.

Original languageEnglish
Title of host publication2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings
Pages173-176
Number of pages4
DOIs
Publication statusPublished - 2012
Event2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Kuala Lumpur
Duration: 19 Sep 201221 Sep 2012

Other

Other2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012
CityKuala Lumpur
Period19/9/1221/9/12

Fingerprint

Transistors
Fabrication
Threshold voltage
Leakage currents
Titanium dioxide
Tungsten
Specifications
Ions
Metals

Keywords

  • 22 nm NMOS
  • high-k/metal gate
  • Scaling down ratio
  • Silvaco

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Afifah Maheran, A. H., N V Visvanathan, P. S. M., Ahmad, I., Elgomati, H. A., Yeop Majlis, B., & Salehuddin, F. (2012). Scaling down of the 32 nm to 22 nm gate length NMOS transistor. In 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings (pp. 173-176). [6417117] https://doi.org/10.1109/SMElec.2012.6417117

Scaling down of the 32 nm to 22 nm gate length NMOS transistor. / Afifah Maheran, A. H.; N V Visvanathan, P. Susthitha Menon; Ahmad, I.; Elgomati, H. A.; Yeop Majlis, Burhanuddin; Salehuddin, F.

2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. p. 173-176 6417117.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Afifah Maheran, AH, N V Visvanathan, PSM, Ahmad, I, Elgomati, HA, Yeop Majlis, B & Salehuddin, F 2012, Scaling down of the 32 nm to 22 nm gate length NMOS transistor. in 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings., 6417117, pp. 173-176, 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012, Kuala Lumpur, 19/9/12. https://doi.org/10.1109/SMElec.2012.6417117
Afifah Maheran AH, N V Visvanathan PSM, Ahmad I, Elgomati HA, Yeop Majlis B, Salehuddin F. Scaling down of the 32 nm to 22 nm gate length NMOS transistor. In 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. p. 173-176. 6417117 https://doi.org/10.1109/SMElec.2012.6417117
Afifah Maheran, A. H. ; N V Visvanathan, P. Susthitha Menon ; Ahmad, I. ; Elgomati, H. A. ; Yeop Majlis, Burhanuddin ; Salehuddin, F. / Scaling down of the 32 nm to 22 nm gate length NMOS transistor. 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. pp. 173-176
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