Review of low power digital delay locked loop (DLL)

Pouya Maroofee, Khairun Nisa’ Minhad, Md. Mamun Ibne Reaz, Noorfazila Kamal, Fazida Hanim Hashim

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Digital delay locked loop (DLL) mainly designed to solve the clock skew in a system. This review presents the advances of DLL structure and its comparison overviews in various applications from past to advance applications. Digital DLL evolutions, parameters and performance characteristic in reducing total power consumption are discussed and shall work as a guideline for the researchers who wish to undertake related research projects.

Original languageEnglish
Pages (from-to)259-265
Number of pages7
JournalJournal of Theoretical and Applied Information Technology
Volume77
Issue number2
Publication statusPublished - 20 Jul 2015

Fingerprint

Clocks
Electric power utilization
Skew
Power Consumption
Review

Keywords

  • Digital delay-locked loops
  • Low power
  • Low power consumption
  • Phase frequency detector

ASJC Scopus subject areas

  • Computer Science(all)
  • Theoretical Computer Science

Cite this

Review of low power digital delay locked loop (DLL). / Maroofee, Pouya; Minhad, Khairun Nisa’; Ibne Reaz, Md. Mamun; Kamal, Noorfazila; Hashim, Fazida Hanim.

In: Journal of Theoretical and Applied Information Technology, Vol. 77, No. 2, 20.07.2015, p. 259-265.

Research output: Contribution to journalArticle

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