Resistorless self-biased curvature compensated sub-1V CMOS bandgap reference

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A Bandgap Voltage Reference (BGR) circuit technique for lower voltage supply operation is presented. It eliminates the need of BGR core and resistors by integrating a two-stage cascode operational amplifier (op-amp) biased with a start-up circuitry with all-MOSFET transistors. The circuit is designed in 0.13μm CMOS process technology, produced a 179mV reference voltage at 27°C with 0.4V supply voltage. The simulated voltage reference achieved 0.02ppm/°C temperature coefficient over -60°C to 45°C temperature range as well as ±170mV over supply voltage variation from 0.1V to 1.2V. The design is simulated and verified with Mentor Graphics.

Original languageEnglish
Title of host publication2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages309-312
Number of pages4
ISBN (Electronic)9781509028894
DOIs
Publication statusPublished - 27 Mar 2017
Event2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 - Putrajaya, Malaysia
Duration: 14 Nov 201616 Nov 2016

Other

Other2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
CountryMalaysia
CityPutrajaya
Period14/11/1616/11/16

Fingerprint

CMOS
Energy gap
curvature
Electric potential
electric potential
operational amplifiers
Networks (circuits)
Operational amplifiers
resistors
low voltage
Resistors
transistors
field effect transistors
Transistors
temperature
Temperature
coefficients

Keywords

  • Curvature compensated
  • Resistorless
  • Self-biased op-amp
  • Sub-1V CMOS bandgap reference
  • Temperature stability
  • Voltage supply stability

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Biomedical Engineering
  • Control and Systems Engineering
  • Hardware and Architecture
  • Computer Networks and Communications
  • Instrumentation

Cite this

Jaafar, K., Kamal, N., Ibne Reaz, M. M., & Sampe, J. (2017). Resistorless self-biased curvature compensated sub-1V CMOS bandgap reference. In 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 (pp. 309-312). [7888059] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICAEES.2016.7888059

Resistorless self-biased curvature compensated sub-1V CMOS bandgap reference. / Jaafar, Khairuddin; Kamal, Noorfazila; Ibne Reaz, Md. Mamun; Sampe, Jahariah.

2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 309-312 7888059.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Jaafar, K, Kamal, N, Ibne Reaz, MM & Sampe, J 2017, Resistorless self-biased curvature compensated sub-1V CMOS bandgap reference. in 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016., 7888059, Institute of Electrical and Electronics Engineers Inc., pp. 309-312, 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016, Putrajaya, Malaysia, 14/11/16. https://doi.org/10.1109/ICAEES.2016.7888059
Jaafar K, Kamal N, Ibne Reaz MM, Sampe J. Resistorless self-biased curvature compensated sub-1V CMOS bandgap reference. In 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 309-312. 7888059 https://doi.org/10.1109/ICAEES.2016.7888059
Jaafar, Khairuddin ; Kamal, Noorfazila ; Ibne Reaz, Md. Mamun ; Sampe, Jahariah. / Resistorless self-biased curvature compensated sub-1V CMOS bandgap reference. 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 309-312
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