Reliable and higher throughput anti-collision technique for RFID UHF tag

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

This paper presents a proposed Reliable and Higher Throughput Anti-collision technique (RHTACT) for Radio Frequency Identification (RFID) Class 0 UHF tag. The RHTACT architecture consists of two main subsystems; Pre RHTACT and Post RHTACT. The Pre RHTACT subsystem is to detect any error in the incoming messages. Then the identification bit (ID) of the no error packet will be fed to the next subsystem. The Post RHTACT subsystem is to identify the tag by using the proposed Lookup Table. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim and synthesized using Xilinix Synthesis Technology. The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) Virtex II. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer for real time verification. Finally the RHTACT architecture is resynthesized using Application Specific Integrated Circuit (ASIC) technology for on-chip implementation. This technology consists of 0.18 μm Library, Synopsys Compiler and tools. From the hardware verification results, it shows that the proposed RHTACT system enables to identify the tags without error at the maximum operating frequency of 80 MHz. The system consumes 13.13mW powers, occupies 11,531 gates and 0.06870 mm2 area with Data arrival time of 2.72 ns.

Original languageEnglish
Pages (from-to)445-449
Number of pages5
JournalWorld Applied Sciences Journal
Volume20
Issue number3
DOIs
Publication statusPublished - 2012
Externally publishedYes

Fingerprint

Radio frequency identification (RFID)
Throughput
Hardware
Computer hardware description languages
Table lookup
Application specific integrated circuits

Keywords

  • Area
  • Class
  • Gates
  • Hardware implementation
  • Power
  • Real time verification
  • Tag

ASJC Scopus subject areas

  • General

Cite this

Reliable and higher throughput anti-collision technique for RFID UHF tag. / Sampe, Jahariah.

In: World Applied Sciences Journal, Vol. 20, No. 3, 2012, p. 445-449.

Research output: Contribution to journalArticle

@article{ac95fbadf72a4457839e6b20cec36fe4,
title = "Reliable and higher throughput anti-collision technique for RFID UHF tag",
abstract = "This paper presents a proposed Reliable and Higher Throughput Anti-collision technique (RHTACT) for Radio Frequency Identification (RFID) Class 0 UHF tag. The RHTACT architecture consists of two main subsystems; Pre RHTACT and Post RHTACT. The Pre RHTACT subsystem is to detect any error in the incoming messages. Then the identification bit (ID) of the no error packet will be fed to the next subsystem. The Post RHTACT subsystem is to identify the tag by using the proposed Lookup Table. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim and synthesized using Xilinix Synthesis Technology. The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) Virtex II. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer for real time verification. Finally the RHTACT architecture is resynthesized using Application Specific Integrated Circuit (ASIC) technology for on-chip implementation. This technology consists of 0.18 μm Library, Synopsys Compiler and tools. From the hardware verification results, it shows that the proposed RHTACT system enables to identify the tags without error at the maximum operating frequency of 80 MHz. The system consumes 13.13mW powers, occupies 11,531 gates and 0.06870 mm2 area with Data arrival time of 2.72 ns.",
keywords = "Area, Class, Gates, Hardware implementation, Power, Real time verification, Tag",
author = "Jahariah Sampe",
year = "2012",
doi = "10.5829/idosi.wasj.2012.20.03.2280",
language = "English",
volume = "20",
pages = "445--449",
journal = "World Applied Sciences Journal",
issn = "1818-4952",
publisher = "International Digital Organization for Scientific Information",
number = "3",

}

TY - JOUR

T1 - Reliable and higher throughput anti-collision technique for RFID UHF tag

AU - Sampe, Jahariah

PY - 2012

Y1 - 2012

N2 - This paper presents a proposed Reliable and Higher Throughput Anti-collision technique (RHTACT) for Radio Frequency Identification (RFID) Class 0 UHF tag. The RHTACT architecture consists of two main subsystems; Pre RHTACT and Post RHTACT. The Pre RHTACT subsystem is to detect any error in the incoming messages. Then the identification bit (ID) of the no error packet will be fed to the next subsystem. The Post RHTACT subsystem is to identify the tag by using the proposed Lookup Table. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim and synthesized using Xilinix Synthesis Technology. The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) Virtex II. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer for real time verification. Finally the RHTACT architecture is resynthesized using Application Specific Integrated Circuit (ASIC) technology for on-chip implementation. This technology consists of 0.18 μm Library, Synopsys Compiler and tools. From the hardware verification results, it shows that the proposed RHTACT system enables to identify the tags without error at the maximum operating frequency of 80 MHz. The system consumes 13.13mW powers, occupies 11,531 gates and 0.06870 mm2 area with Data arrival time of 2.72 ns.

AB - This paper presents a proposed Reliable and Higher Throughput Anti-collision technique (RHTACT) for Radio Frequency Identification (RFID) Class 0 UHF tag. The RHTACT architecture consists of two main subsystems; Pre RHTACT and Post RHTACT. The Pre RHTACT subsystem is to detect any error in the incoming messages. Then the identification bit (ID) of the no error packet will be fed to the next subsystem. The Post RHTACT subsystem is to identify the tag by using the proposed Lookup Table. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim and synthesized using Xilinix Synthesis Technology. The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) Virtex II. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer for real time verification. Finally the RHTACT architecture is resynthesized using Application Specific Integrated Circuit (ASIC) technology for on-chip implementation. This technology consists of 0.18 μm Library, Synopsys Compiler and tools. From the hardware verification results, it shows that the proposed RHTACT system enables to identify the tags without error at the maximum operating frequency of 80 MHz. The system consumes 13.13mW powers, occupies 11,531 gates and 0.06870 mm2 area with Data arrival time of 2.72 ns.

KW - Area

KW - Class

KW - Gates

KW - Hardware implementation

KW - Power

KW - Real time verification

KW - Tag

UR - http://www.scopus.com/inward/record.url?scp=84871556963&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84871556963&partnerID=8YFLogxK

U2 - 10.5829/idosi.wasj.2012.20.03.2280

DO - 10.5829/idosi.wasj.2012.20.03.2280

M3 - Article

AN - SCOPUS:84871556963

VL - 20

SP - 445

EP - 449

JO - World Applied Sciences Journal

JF - World Applied Sciences Journal

SN - 1818-4952

IS - 3

ER -