Reliable and cost effective anti-collision technique for RFID UHF tag

Jahariah Sampe, Khairul Parman Zakaria, Fazida Hanim Hashim, Masuri Othman

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

This paper presents a proposed Reliable and Cost Effective Anti-collision technique (RCEAT) for Radio Frequency Identification (RFID) Class 0 UHF tag. The RCEAT architecture consists of two main subsystems; PreRCEAT and PostRCEAT. The PreRCEAT subsystem is to detect any error in the incoming messages. Then the identification bit (ID) of the no error packet will be fed to the next subsystem. The PostRCEAT subsystem is to identify the tag by using the proposed Fast-search Lookup Table. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim and synthesized using Xilinix Synthesis Technology. The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) Virtex II. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer for real time verification. Finally the RCEAT architecture is resynthesized using Application Specific Integrated Circuit (ASIC) technology for on-chip implementation. This technology consists of 0.18 m Library, Synopsys Compiler and tools. From the hardware verification results, it shows that the proposed RCEAT system enables to identify the tags without error at the maximum operating frequency of 180MHz. The system consumes 7.578 mW powers, occupies 6,041 gates and 0.0375 mm 2 area with Data arrival time of 2.31 ns.

Original languageEnglish
Title of host publication2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011
DOIs
Publication statusPublished - 2011
Event2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011 - Kuala Lumpur
Duration: 19 Apr 201121 Apr 2011

Other

Other2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011
CityKuala Lumpur
Period19/4/1121/4/11

Fingerprint

Radio Frequency Identification
Radio frequency identification (RFID)
Collision
Subsystem
Costs
Hardware
Computer hardware description languages
Table lookup
Grid
Application specific integrated circuits
Time of Arrival
Look-up Table
Integrated Circuits
Compiler
Waveform
Chip
Synthesis
Logic
Output
Architecture

ASJC Scopus subject areas

  • Control and Optimization
  • Modelling and Simulation

Cite this

Sampe, J., Zakaria, K. P., Hashim, F. H., & Othman, M. (2011). Reliable and cost effective anti-collision technique for RFID UHF tag. In 2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011 [5775465] https://doi.org/10.1109/ICMSAO.2011.5775465

Reliable and cost effective anti-collision technique for RFID UHF tag. / Sampe, Jahariah; Zakaria, Khairul Parman; Hashim, Fazida Hanim; Othman, Masuri.

2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011. 2011. 5775465.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Sampe, J, Zakaria, KP, Hashim, FH & Othman, M 2011, Reliable and cost effective anti-collision technique for RFID UHF tag. in 2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011., 5775465, 2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011, Kuala Lumpur, 19/4/11. https://doi.org/10.1109/ICMSAO.2011.5775465
Sampe J, Zakaria KP, Hashim FH, Othman M. Reliable and cost effective anti-collision technique for RFID UHF tag. In 2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011. 2011. 5775465 https://doi.org/10.1109/ICMSAO.2011.5775465
Sampe, Jahariah ; Zakaria, Khairul Parman ; Hashim, Fazida Hanim ; Othman, Masuri. / Reliable and cost effective anti-collision technique for RFID UHF tag. 2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011. 2011.
@inproceedings{766cf9d5e4024a9db9b515919f3dcf82,
title = "Reliable and cost effective anti-collision technique for RFID UHF tag",
abstract = "This paper presents a proposed Reliable and Cost Effective Anti-collision technique (RCEAT) for Radio Frequency Identification (RFID) Class 0 UHF tag. The RCEAT architecture consists of two main subsystems; PreRCEAT and PostRCEAT. The PreRCEAT subsystem is to detect any error in the incoming messages. Then the identification bit (ID) of the no error packet will be fed to the next subsystem. The PostRCEAT subsystem is to identify the tag by using the proposed Fast-search Lookup Table. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim and synthesized using Xilinix Synthesis Technology. The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) Virtex II. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer for real time verification. Finally the RCEAT architecture is resynthesized using Application Specific Integrated Circuit (ASIC) technology for on-chip implementation. This technology consists of 0.18 m Library, Synopsys Compiler and tools. From the hardware verification results, it shows that the proposed RCEAT system enables to identify the tags without error at the maximum operating frequency of 180MHz. The system consumes 7.578 mW powers, occupies 6,041 gates and 0.0375 mm 2 area with Data arrival time of 2.31 ns.",
author = "Jahariah Sampe and Zakaria, {Khairul Parman} and Hashim, {Fazida Hanim} and Masuri Othman",
year = "2011",
doi = "10.1109/ICMSAO.2011.5775465",
language = "English",
isbn = "9781457700057",
booktitle = "2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011",

}

TY - GEN

T1 - Reliable and cost effective anti-collision technique for RFID UHF tag

AU - Sampe, Jahariah

AU - Zakaria, Khairul Parman

AU - Hashim, Fazida Hanim

AU - Othman, Masuri

PY - 2011

Y1 - 2011

N2 - This paper presents a proposed Reliable and Cost Effective Anti-collision technique (RCEAT) for Radio Frequency Identification (RFID) Class 0 UHF tag. The RCEAT architecture consists of two main subsystems; PreRCEAT and PostRCEAT. The PreRCEAT subsystem is to detect any error in the incoming messages. Then the identification bit (ID) of the no error packet will be fed to the next subsystem. The PostRCEAT subsystem is to identify the tag by using the proposed Fast-search Lookup Table. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim and synthesized using Xilinix Synthesis Technology. The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) Virtex II. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer for real time verification. Finally the RCEAT architecture is resynthesized using Application Specific Integrated Circuit (ASIC) technology for on-chip implementation. This technology consists of 0.18 m Library, Synopsys Compiler and tools. From the hardware verification results, it shows that the proposed RCEAT system enables to identify the tags without error at the maximum operating frequency of 180MHz. The system consumes 7.578 mW powers, occupies 6,041 gates and 0.0375 mm 2 area with Data arrival time of 2.31 ns.

AB - This paper presents a proposed Reliable and Cost Effective Anti-collision technique (RCEAT) for Radio Frequency Identification (RFID) Class 0 UHF tag. The RCEAT architecture consists of two main subsystems; PreRCEAT and PostRCEAT. The PreRCEAT subsystem is to detect any error in the incoming messages. Then the identification bit (ID) of the no error packet will be fed to the next subsystem. The PostRCEAT subsystem is to identify the tag by using the proposed Fast-search Lookup Table. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim and synthesized using Xilinix Synthesis Technology. The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) Virtex II. The output waveforms from the FPGA have been tested on the Tektronix Logic Analyzer for real time verification. Finally the RCEAT architecture is resynthesized using Application Specific Integrated Circuit (ASIC) technology for on-chip implementation. This technology consists of 0.18 m Library, Synopsys Compiler and tools. From the hardware verification results, it shows that the proposed RCEAT system enables to identify the tags without error at the maximum operating frequency of 180MHz. The system consumes 7.578 mW powers, occupies 6,041 gates and 0.0375 mm 2 area with Data arrival time of 2.31 ns.

UR - http://www.scopus.com/inward/record.url?scp=79959628123&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79959628123&partnerID=8YFLogxK

U2 - 10.1109/ICMSAO.2011.5775465

DO - 10.1109/ICMSAO.2011.5775465

M3 - Conference contribution

SN - 9781457700057

BT - 2011 4th International Conference on Modeling, Simulation and Applied Optimization, ICMSAO 2011

ER -