On-chip implementation of high speed and high resolution pipeline radix 2 FFT algorithm

N. Mahdavi, R. Teymourzadeh, Masuri Bin Othman

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    2 Citations (Scopus)

    Abstract

    A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement the high speed FFT on FPGA. The proposed FFT algorithm shows the latency of (N/2 log2 N) + 11. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.

    Original languageEnglish
    Title of host publication2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007
    Pages1286-1288
    Number of pages3
    DOIs
    Publication statusPublished - 2007
    Event2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007 - Kuala Lumpur
    Duration: 25 Nov 200728 Nov 2007

    Other

    Other2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007
    CityKuala Lumpur
    Period25/11/0728/11/07

    Fingerprint

    Fast Fourier transforms
    Pipelines
    Field programmable gate arrays (FPGA)

    ASJC Scopus subject areas

    • Artificial Intelligence
    • Control and Systems Engineering

    Cite this

    Mahdavi, N., Teymourzadeh, R., & Othman, M. B. (2007). On-chip implementation of high speed and high resolution pipeline radix 2 FFT algorithm. In 2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007 (pp. 1286-1288). [4658591] https://doi.org/10.1109/ICIAS.2007.4658591

    On-chip implementation of high speed and high resolution pipeline radix 2 FFT algorithm. / Mahdavi, N.; Teymourzadeh, R.; Othman, Masuri Bin.

    2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007. 2007. p. 1286-1288 4658591.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Mahdavi, N, Teymourzadeh, R & Othman, MB 2007, On-chip implementation of high speed and high resolution pipeline radix 2 FFT algorithm. in 2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007., 4658591, pp. 1286-1288, 2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007, Kuala Lumpur, 25/11/07. https://doi.org/10.1109/ICIAS.2007.4658591
    Mahdavi N, Teymourzadeh R, Othman MB. On-chip implementation of high speed and high resolution pipeline radix 2 FFT algorithm. In 2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007. 2007. p. 1286-1288. 4658591 https://doi.org/10.1109/ICIAS.2007.4658591
    Mahdavi, N. ; Teymourzadeh, R. ; Othman, Masuri Bin. / On-chip implementation of high speed and high resolution pipeline radix 2 FFT algorithm. 2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007. 2007. pp. 1286-1288
    @inproceedings{bdd194eed39c4fb490ee97e1eaf36ce1,
    title = "On-chip implementation of high speed and high resolution pipeline radix 2 FFT algorithm",
    abstract = "A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement the high speed FFT on FPGA. The proposed FFT algorithm shows the latency of (N/2 log2 N) + 11. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.",
    author = "N. Mahdavi and R. Teymourzadeh and Othman, {Masuri Bin}",
    year = "2007",
    doi = "10.1109/ICIAS.2007.4658591",
    language = "English",
    isbn = "1424413559",
    pages = "1286--1288",
    booktitle = "2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007",

    }

    TY - GEN

    T1 - On-chip implementation of high speed and high resolution pipeline radix 2 FFT algorithm

    AU - Mahdavi, N.

    AU - Teymourzadeh, R.

    AU - Othman, Masuri Bin

    PY - 2007

    Y1 - 2007

    N2 - A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement the high speed FFT on FPGA. The proposed FFT algorithm shows the latency of (N/2 log2 N) + 11. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.

    AB - A new on-chip implementation of Fast Fourier Transform (FFT) based on Radix 2 is presented. The pipeline and parallel approaches are combined to introduce a new high speed FFT algorithm which increases resolution by using floating point calculations in its structures. The design has the merits of low complexity and high speed performance. Furthermore, latency reduction is an important issue to implement the high speed FFT on FPGA. The proposed FFT algorithm shows the latency of (N/2 log2 N) + 11. Moreover, this algorithm has the advantage of low mean squared error (MSE) of 0.0001 which is preferable to Radix 2 FFT.

    UR - http://www.scopus.com/inward/record.url?scp=57949107734&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=57949107734&partnerID=8YFLogxK

    U2 - 10.1109/ICIAS.2007.4658591

    DO - 10.1109/ICIAS.2007.4658591

    M3 - Conference contribution

    AN - SCOPUS:57949107734

    SN - 1424413559

    SN - 9781424413553

    SP - 1286

    EP - 1288

    BT - 2007 International Conference on Intelligent and Advanced Systems, ICIAS 2007

    ER -