On chip communication architecture power estimation in high frequency high power model

Khalid B. Suliman, Rashid A. Saeed, Raed A. Alsaqour

Research output: Contribution to journalArticle

Abstract

System-on-Chip (SoC) on chip communication architecture solved the problem of how to interconnect hundreds of processing element (PE) and storage element (SE) inside one chip, but in the other hand it introduced power consumption hindrance in the communication elements such as bridges, bus wire, bus interface and arbiters to the overall power usage in the chip. Various power estimation techniques was introduced mostly focusing only on the power consumed in parts of the SoC communication architecture, like the global bus interconnect or the bus wire those techniques only tackles part of the overall consumed power. This paper proposes a system level power consumption estimation model for SoC for all of the communication elements with high frequency effects and system communication activity consideration.

Original languageEnglish
Pages (from-to)5126-5131
Number of pages6
JournalARPN Journal of Engineering and Applied Sciences
Volume10
Issue number12
Publication statusPublished - 2015

Fingerprint

Communication
Electric power utilization
Wire
Processing
System-on-chip

Keywords

  • On chip communication
  • Power consumption
  • Power estimation
  • System-on-ship

ASJC Scopus subject areas

  • Engineering(all)

Cite this

On chip communication architecture power estimation in high frequency high power model. / Suliman, Khalid B.; Saeed, Rashid A.; Alsaqour, Raed A.

In: ARPN Journal of Engineering and Applied Sciences, Vol. 10, No. 12, 2015, p. 5126-5131.

Research output: Contribution to journalArticle

Suliman, Khalid B. ; Saeed, Rashid A. ; Alsaqour, Raed A. / On chip communication architecture power estimation in high frequency high power model. In: ARPN Journal of Engineering and Applied Sciences. 2015 ; Vol. 10, No. 12. pp. 5126-5131.
@article{3f7c8785ca954d24a68738cb4c922b8a,
title = "On chip communication architecture power estimation in high frequency high power model",
abstract = "System-on-Chip (SoC) on chip communication architecture solved the problem of how to interconnect hundreds of processing element (PE) and storage element (SE) inside one chip, but in the other hand it introduced power consumption hindrance in the communication elements such as bridges, bus wire, bus interface and arbiters to the overall power usage in the chip. Various power estimation techniques was introduced mostly focusing only on the power consumed in parts of the SoC communication architecture, like the global bus interconnect or the bus wire those techniques only tackles part of the overall consumed power. This paper proposes a system level power consumption estimation model for SoC for all of the communication elements with high frequency effects and system communication activity consideration.",
keywords = "On chip communication, Power consumption, Power estimation, System-on-ship",
author = "Suliman, {Khalid B.} and Saeed, {Rashid A.} and Alsaqour, {Raed A.}",
year = "2015",
language = "English",
volume = "10",
pages = "5126--5131",
journal = "ARPN Journal of Engineering and Applied Sciences",
issn = "1819-6608",
publisher = "Asian Research Publishing Network (ARPN)",
number = "12",

}

TY - JOUR

T1 - On chip communication architecture power estimation in high frequency high power model

AU - Suliman, Khalid B.

AU - Saeed, Rashid A.

AU - Alsaqour, Raed A.

PY - 2015

Y1 - 2015

N2 - System-on-Chip (SoC) on chip communication architecture solved the problem of how to interconnect hundreds of processing element (PE) and storage element (SE) inside one chip, but in the other hand it introduced power consumption hindrance in the communication elements such as bridges, bus wire, bus interface and arbiters to the overall power usage in the chip. Various power estimation techniques was introduced mostly focusing only on the power consumed in parts of the SoC communication architecture, like the global bus interconnect or the bus wire those techniques only tackles part of the overall consumed power. This paper proposes a system level power consumption estimation model for SoC for all of the communication elements with high frequency effects and system communication activity consideration.

AB - System-on-Chip (SoC) on chip communication architecture solved the problem of how to interconnect hundreds of processing element (PE) and storage element (SE) inside one chip, but in the other hand it introduced power consumption hindrance in the communication elements such as bridges, bus wire, bus interface and arbiters to the overall power usage in the chip. Various power estimation techniques was introduced mostly focusing only on the power consumed in parts of the SoC communication architecture, like the global bus interconnect or the bus wire those techniques only tackles part of the overall consumed power. This paper proposes a system level power consumption estimation model for SoC for all of the communication elements with high frequency effects and system communication activity consideration.

KW - On chip communication

KW - Power consumption

KW - Power estimation

KW - System-on-ship

UR - http://www.scopus.com/inward/record.url?scp=84937047010&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84937047010&partnerID=8YFLogxK

M3 - Article

VL - 10

SP - 5126

EP - 5131

JO - ARPN Journal of Engineering and Applied Sciences

JF - ARPN Journal of Engineering and Applied Sciences

SN - 1819-6608

IS - 12

ER -