Numerical study of side gate junction-less transistor in on state

Arash Dehzangi, Farhad Larki, Burhanuddin Yeop Majlis, M. N. Hamidon, Manizheh Navasery, Elham Gharibshahi, Nasrin Khalilzadeh, Mohammadmahdi Vakilian, Elias B. Saion

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Side gate p-type Junctionless Silicon transistor is fabricated by AFM nanolithography on low-doped (105 cm-3) SOI wafer. In this work, the simulation characteristic of the device using TCAD Sentaurus in on state will be studied. The results show that the device is the pinch off transistor, works in on state for zero gate voltage in depletion mode. Negative gate voltage drives the device into on state, but unable to make significant effect on drain current as accmulation mode. Simulation results for valence band energy, electric field and hole density are investigated along the active regions. The influence of the electric field due to the applied voltages of VDS and VG on charge distribution is much more when the device operates at the saturation region. The hole quasi-Fermi level has a positive slope showing the current flows from source to drain.

Original languageEnglish
Title of host publicationProceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics
Pages398-401
Number of pages4
DOIs
Publication statusPublished - 2013
Event2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013 - Langkawi
Duration: 25 Sep 201327 Sep 2013

Other

Other2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013
CityLangkawi
Period25/9/1327/9/13

Fingerprint

Transistors
Electric potential
Electric fields
Gates (transistor)
Nanolithography
Drain current
Charge distribution
Valence bands
Fermi level
Silicon

Keywords

  • hole density distribution
  • Side gate Junctionless Transistors (SGJLT)
  • valence band energy

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Dehzangi, A., Larki, F., Yeop Majlis, B., Hamidon, M. N., Navasery, M., Gharibshahi, E., ... Saion, E. B. (2013). Numerical study of side gate junction-less transistor in on state. In Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics (pp. 398-401). [6706575] https://doi.org/10.1109/RSM.2013.6706575

Numerical study of side gate junction-less transistor in on state. / Dehzangi, Arash; Larki, Farhad; Yeop Majlis, Burhanuddin; Hamidon, M. N.; Navasery, Manizheh; Gharibshahi, Elham; Khalilzadeh, Nasrin; Vakilian, Mohammadmahdi; Saion, Elias B.

Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics. 2013. p. 398-401 6706575.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Dehzangi, A, Larki, F, Yeop Majlis, B, Hamidon, MN, Navasery, M, Gharibshahi, E, Khalilzadeh, N, Vakilian, M & Saion, EB 2013, Numerical study of side gate junction-less transistor in on state. in Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics., 6706575, pp. 398-401, 2013 IEEE Regional Symposium on Micro and Nano Electronics, RSM 2013, Langkawi, 25/9/13. https://doi.org/10.1109/RSM.2013.6706575
Dehzangi A, Larki F, Yeop Majlis B, Hamidon MN, Navasery M, Gharibshahi E et al. Numerical study of side gate junction-less transistor in on state. In Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics. 2013. p. 398-401. 6706575 https://doi.org/10.1109/RSM.2013.6706575
Dehzangi, Arash ; Larki, Farhad ; Yeop Majlis, Burhanuddin ; Hamidon, M. N. ; Navasery, Manizheh ; Gharibshahi, Elham ; Khalilzadeh, Nasrin ; Vakilian, Mohammadmahdi ; Saion, Elias B. / Numerical study of side gate junction-less transistor in on state. Proceedings - RSM 2013: 2013 IEEE Regional Symposium on Micro and Nano Electronics. 2013. pp. 398-401
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