Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state

A. Dehzangi, F. Larki, S. D. Hutagalung, E. B. Saion, A. M. Abdullah, M. N. Hamidon, Burhanuddin Yeop Majlis, S. Kakooei, M. Navaseri, A. Kharazmi

Research output: Contribution to journalArticle

10 Citations (Scopus)

Abstract

A side gate p-type junctionless silicon transistor is fabricated by atomic force microscopy nanolithography using a anisotropic potassium hydroxide wet etching process on low doped (10 5cm -3) silicon-on-insulator wafer. The structure is a gated resistor and turns off based on a pinch-off effect principle, when essential positive gate voltage is applied and made a sufficiently large barrier in the gating region. Negative gate voltage is unable to make a significant impact on drain current to drive the device into accumulation mode. The experimental transfer characteristic is investigated and compared with the simulation result for positive gate voltage. 'On/off' ratio and subthreshold swing were also measured. The numerical study of the device in 'off' state is investigated based on the variation of majority and minority carriers' density and recombination generation in the active region of the device, which offers more understanding of the device operation and also for previous works.

Original languageEnglish
Pages (from-to)981-985
Number of pages5
JournalMicro and Nano Letters
Volume7
Issue number9
DOIs
Publication statusPublished - Sep 2012

Fingerprint

silicon transistors
Silicon
Transistors
Electric potential
Gates (transistor)
Nanolithography
Potassium hydroxide
electric potential
Wet etching
Drain current
potassium hydroxides
Resistors
majority carriers
Carrier concentration
Atomic force microscopy
minority carriers
resistors
insulators
etching
atomic force microscopy

ASJC Scopus subject areas

  • Materials Science(all)
  • Condensed Matter Physics
  • Bioengineering
  • Biomedical Engineering

Cite this

Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state. / Dehzangi, A.; Larki, F.; Hutagalung, S. D.; Saion, E. B.; Abdullah, A. M.; Hamidon, M. N.; Yeop Majlis, Burhanuddin; Kakooei, S.; Navaseri, M.; Kharazmi, A.

In: Micro and Nano Letters, Vol. 7, No. 9, 09.2012, p. 981-985.

Research output: Contribution to journalArticle

Dehzangi, A, Larki, F, Hutagalung, SD, Saion, EB, Abdullah, AM, Hamidon, MN, Yeop Majlis, B, Kakooei, S, Navaseri, M & Kharazmi, A 2012, 'Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state', Micro and Nano Letters, vol. 7, no. 9, pp. 981-985. https://doi.org/10.1049/mnl.2012.0590
Dehzangi, A. ; Larki, F. ; Hutagalung, S. D. ; Saion, E. B. ; Abdullah, A. M. ; Hamidon, M. N. ; Yeop Majlis, Burhanuddin ; Kakooei, S. ; Navaseri, M. ; Kharazmi, A. / Numerical investigation and comparison with experimental characterisation of side gate p-type junctionless silicon transistor in pinch-off state. In: Micro and Nano Letters. 2012 ; Vol. 7, No. 9. pp. 981-985.
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