Multiple nanowire gate field effect transistors

Saleem H. Zaidi, A. K. Sharma, R. Marquardt, S. L. Lucero, P. M. Varangis

Research output: Chapter in Book/Report/Conference proceedingConference contribution

3 Citations (Scopus)

Abstract

Novel metal oxide semiconductor field effect transistor (MOSFET) architectures aimed at sub IV operation with enhanced current driving capability are reported. In our design, the planar channel region in a conventional MOSFET is replaced by an array of isolated Si wires. Directional metal coverage of the two sidewalls and the top surface of each Si wire help achieve enhanced gate control. Sub IV operation is achieved by reducing cross-sectional wire diameters to ∼0.05 μm. Since the conventional optical lithography techniques lack patterning resolution at this scale, a mix and match approach with interferometric lithography was employed. Super-resolution capability of interferometric lithography was applied to pattern nanoscale Si wires, while optical lithography was used to pattern non-critical device levels. Drain current versus gate voltage measurements of planar and wire MOSFETs demonstrated the superiority of the multiple nanowire gate design. Increasing the number of 0.05-μm diameter wires significantly increased current flow in the channel region without sacrificing the lowvoltage operation. The mix and match approach for patterning critical level nanoscale features represents a low-cost complement to optical lithography.

Original languageEnglish
Title of host publicationProceedings of the IEEE Conference on Nanotechnology
PublisherIEEE Computer Society
Pages189-194
Number of pages6
Volume2001-January
ISBN (Print)0780372158
DOIs
Publication statusPublished - 2001
Externally publishedYes
Event1st IEEE Conference on Nanotechnology, IEEE-NANO 2001 - Maui, United States
Duration: 28 Oct 200130 Oct 2001

Other

Other1st IEEE Conference on Nanotechnology, IEEE-NANO 2001
CountryUnited States
CityMaui
Period28/10/0130/10/01

Fingerprint

Gates (transistor)
Nanowires
nanowires
field effect transistors
wire
Wire
lithography
Photolithography
MOSFET devices
metal oxide semiconductors
Lithography
Drain current
Voltage measurement
complement
electrical measurement
Metals
metals
Costs

ASJC Scopus subject areas

  • Bioengineering
  • Electrical and Electronic Engineering
  • Materials Chemistry
  • Condensed Matter Physics

Cite this

Zaidi, S. H., Sharma, A. K., Marquardt, R., Lucero, S. L., & Varangis, P. M. (2001). Multiple nanowire gate field effect transistors. In Proceedings of the IEEE Conference on Nanotechnology (Vol. 2001-January, pp. 189-194). [966417] IEEE Computer Society. https://doi.org/10.1109/NANO.2001.966417

Multiple nanowire gate field effect transistors. / Zaidi, Saleem H.; Sharma, A. K.; Marquardt, R.; Lucero, S. L.; Varangis, P. M.

Proceedings of the IEEE Conference on Nanotechnology. Vol. 2001-January IEEE Computer Society, 2001. p. 189-194 966417.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Zaidi, SH, Sharma, AK, Marquardt, R, Lucero, SL & Varangis, PM 2001, Multiple nanowire gate field effect transistors. in Proceedings of the IEEE Conference on Nanotechnology. vol. 2001-January, 966417, IEEE Computer Society, pp. 189-194, 1st IEEE Conference on Nanotechnology, IEEE-NANO 2001, Maui, United States, 28/10/01. https://doi.org/10.1109/NANO.2001.966417
Zaidi SH, Sharma AK, Marquardt R, Lucero SL, Varangis PM. Multiple nanowire gate field effect transistors. In Proceedings of the IEEE Conference on Nanotechnology. Vol. 2001-January. IEEE Computer Society. 2001. p. 189-194. 966417 https://doi.org/10.1109/NANO.2001.966417
Zaidi, Saleem H. ; Sharma, A. K. ; Marquardt, R. ; Lucero, S. L. ; Varangis, P. M. / Multiple nanowire gate field effect transistors. Proceedings of the IEEE Conference on Nanotechnology. Vol. 2001-January IEEE Computer Society, 2001. pp. 189-194
@inproceedings{037f261bb3284eebab87e96a2294e2ce,
title = "Multiple nanowire gate field effect transistors",
abstract = "Novel metal oxide semiconductor field effect transistor (MOSFET) architectures aimed at sub IV operation with enhanced current driving capability are reported. In our design, the planar channel region in a conventional MOSFET is replaced by an array of isolated Si wires. Directional metal coverage of the two sidewalls and the top surface of each Si wire help achieve enhanced gate control. Sub IV operation is achieved by reducing cross-sectional wire diameters to ∼0.05 μm. Since the conventional optical lithography techniques lack patterning resolution at this scale, a mix and match approach with interferometric lithography was employed. Super-resolution capability of interferometric lithography was applied to pattern nanoscale Si wires, while optical lithography was used to pattern non-critical device levels. Drain current versus gate voltage measurements of planar and wire MOSFETs demonstrated the superiority of the multiple nanowire gate design. Increasing the number of 0.05-μm diameter wires significantly increased current flow in the channel region without sacrificing the lowvoltage operation. The mix and match approach for patterning critical level nanoscale features represents a low-cost complement to optical lithography.",
author = "Zaidi, {Saleem H.} and Sharma, {A. K.} and R. Marquardt and Lucero, {S. L.} and Varangis, {P. M.}",
year = "2001",
doi = "10.1109/NANO.2001.966417",
language = "English",
isbn = "0780372158",
volume = "2001-January",
pages = "189--194",
booktitle = "Proceedings of the IEEE Conference on Nanotechnology",
publisher = "IEEE Computer Society",

}

TY - GEN

T1 - Multiple nanowire gate field effect transistors

AU - Zaidi, Saleem H.

AU - Sharma, A. K.

AU - Marquardt, R.

AU - Lucero, S. L.

AU - Varangis, P. M.

PY - 2001

Y1 - 2001

N2 - Novel metal oxide semiconductor field effect transistor (MOSFET) architectures aimed at sub IV operation with enhanced current driving capability are reported. In our design, the planar channel region in a conventional MOSFET is replaced by an array of isolated Si wires. Directional metal coverage of the two sidewalls and the top surface of each Si wire help achieve enhanced gate control. Sub IV operation is achieved by reducing cross-sectional wire diameters to ∼0.05 μm. Since the conventional optical lithography techniques lack patterning resolution at this scale, a mix and match approach with interferometric lithography was employed. Super-resolution capability of interferometric lithography was applied to pattern nanoscale Si wires, while optical lithography was used to pattern non-critical device levels. Drain current versus gate voltage measurements of planar and wire MOSFETs demonstrated the superiority of the multiple nanowire gate design. Increasing the number of 0.05-μm diameter wires significantly increased current flow in the channel region without sacrificing the lowvoltage operation. The mix and match approach for patterning critical level nanoscale features represents a low-cost complement to optical lithography.

AB - Novel metal oxide semiconductor field effect transistor (MOSFET) architectures aimed at sub IV operation with enhanced current driving capability are reported. In our design, the planar channel region in a conventional MOSFET is replaced by an array of isolated Si wires. Directional metal coverage of the two sidewalls and the top surface of each Si wire help achieve enhanced gate control. Sub IV operation is achieved by reducing cross-sectional wire diameters to ∼0.05 μm. Since the conventional optical lithography techniques lack patterning resolution at this scale, a mix and match approach with interferometric lithography was employed. Super-resolution capability of interferometric lithography was applied to pattern nanoscale Si wires, while optical lithography was used to pattern non-critical device levels. Drain current versus gate voltage measurements of planar and wire MOSFETs demonstrated the superiority of the multiple nanowire gate design. Increasing the number of 0.05-μm diameter wires significantly increased current flow in the channel region without sacrificing the lowvoltage operation. The mix and match approach for patterning critical level nanoscale features represents a low-cost complement to optical lithography.

UR - http://www.scopus.com/inward/record.url?scp=84949233216&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84949233216&partnerID=8YFLogxK

U2 - 10.1109/NANO.2001.966417

DO - 10.1109/NANO.2001.966417

M3 - Conference contribution

SN - 0780372158

VL - 2001-January

SP - 189

EP - 194

BT - Proceedings of the IEEE Conference on Nanotechnology

PB - IEEE Computer Society

ER -