MOS implementation of Manchester carry chain adder for VLSI designer library

Research output: Contribution to journalArticle

Abstract

Adder is used to sum two binary numbers and the carry input signals. Adders are widely used in variance electronic or signal processing tasks. A wide variety of adder implementations are available to serve different speed/density requirements. The Manchester carry chain adder is chosen because it is fast and gives constant rise time and delay time for all the sum and carry output signals. Simulations were done to determine the best Manchester carry chain adder circuitry that produces the best performances for VLSI designer library by using Tanner Tools Pro. The two-micron technology with the channel length, equal to 2μm is used for the simulation. The 2-bit dynamic stage Manchester carry chain adder with maximum frequency 125MHz gives constant rise time, fall time and delay time for the carry and sum outputs. The dynamic stage Manchester carry chain adder contains a total of 41 Metal Oxide Semiconductor Transistor (MOS). The dynamic stage Manchester carry chain adder is selected for the VLSI designer library.

Original languageEnglish
Pages (from-to)1069-1076
Number of pages8
JournalWSEAS Transactions on Circuits and Systems
Volume4
Issue number9
Publication statusPublished - Sep 2005
Externally publishedYes

Fingerprint

Adders
Transistors
Metals
Time delay
Oxide semiconductors
Signal processing

Keywords

  • Manchester carry chain adder
  • MOS
  • VLSI design
  • VLSI designer library

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

MOS implementation of Manchester carry chain adder for VLSI designer library. / Pang, W. L.; Ibne Reaz, Md. Mamun.

In: WSEAS Transactions on Circuits and Systems, Vol. 4, No. 9, 09.2005, p. 1069-1076.

Research output: Contribution to journalArticle

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