Modelling of process parameters for 32nm PMOS transistor using Taguchi method

H. A. Elgomati, Burhanuddin Yeop Majlis, A. M Abdul Hamid, P. Susthitha Menon N V Visvanathan, I. Ahmad

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

As CMOS technology scales down to the nanometer level process variation can produce deviation in device parameters which affect circuit performance. In this paper, we investigate the effect of seven process parameters and two process noise parameters on threshold voltage (Vth) in a 32nm PMOS transistor. Using Taguchi's experimental robust design strategy seven process parameters were assigned to 7 columns of the L18 orthogonal array to conduct 18 simulation runs. Fabrication of the 32nm PMOS transistor was simulated by using the fabrication tool ATHENA and electrical characterization was simulated using ATLAS. These simulators were used for computing Vth simulations for each row of the L18 array with 4 combinations of the 2 noise factors. Taguchi's nominal-the-best S/N ratio was used as the objective functions for the minimization of variance in Vth. The best settings of process parameters were determined using Analysis of Mean (ANOM) and Analysis of Variance (ANOVA) for reducing the variability of Vth. The best settings were used for verification simulations and the results showed that the Vth values had the least variance and the mean value could be adjusted to-0.103V +-0.003 for PMOS, which is well within ITRS specifications.

Original languageEnglish
Title of host publicationProceedings - 6th Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2012
Pages40-45
Number of pages6
DOIs
Publication statusPublished - 2012
Event6th Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2012 - Bali
Duration: 29 May 201231 May 2012

Other

Other6th Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2012
CityBali
Period29/5/1231/5/12

Fingerprint

Taguchi Method
Taguchi methods
Process Parameters
Transistors
Fabrication
Analysis of variance (ANOVA)
Threshold voltage
Modeling
Noise Factor
Process Variation
Simulation
Orthogonal Array
Robust Design
Simulators
Analysis of variance
Specifications
Mean Value
Categorical or nominal
Networks (circuits)
Simulator

Keywords

  • 32nm PMOS
  • ANOM
  • ANOVA
  • compensation implantations
  • L18 orthogonal array
  • Taguchi Method
  • Threshold voltage

ASJC Scopus subject areas

  • Modelling and Simulation

Cite this

Elgomati, H. A., Yeop Majlis, B., Hamid, A. M. A., N V Visvanathan, P. S. M., & Ahmad, I. (2012). Modelling of process parameters for 32nm PMOS transistor using Taguchi method. In Proceedings - 6th Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2012 (pp. 40-45). [6243918] https://doi.org/10.1109/AMS.2012.22

Modelling of process parameters for 32nm PMOS transistor using Taguchi method. / Elgomati, H. A.; Yeop Majlis, Burhanuddin; Hamid, A. M Abdul; N V Visvanathan, P. Susthitha Menon; Ahmad, I.

Proceedings - 6th Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2012. 2012. p. 40-45 6243918.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Elgomati, HA, Yeop Majlis, B, Hamid, AMA, N V Visvanathan, PSM & Ahmad, I 2012, Modelling of process parameters for 32nm PMOS transistor using Taguchi method. in Proceedings - 6th Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2012., 6243918, pp. 40-45, 6th Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2012, Bali, 29/5/12. https://doi.org/10.1109/AMS.2012.22
Elgomati HA, Yeop Majlis B, Hamid AMA, N V Visvanathan PSM, Ahmad I. Modelling of process parameters for 32nm PMOS transistor using Taguchi method. In Proceedings - 6th Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2012. 2012. p. 40-45. 6243918 https://doi.org/10.1109/AMS.2012.22
Elgomati, H. A. ; Yeop Majlis, Burhanuddin ; Hamid, A. M Abdul ; N V Visvanathan, P. Susthitha Menon ; Ahmad, I. / Modelling of process parameters for 32nm PMOS transistor using Taguchi method. Proceedings - 6th Asia International Conference on Mathematical Modelling and Computer Simulation, AMS 2012. 2012. pp. 40-45
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