Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method

Husam Ahmed Elgomati, Burhanuddin Yeop Majlis, Ibrahim Ahmad

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilicon thickness and silicide annealing time. The setting of process parameters were determined by Taguchi method L18 experimental design. From there, the level of importance of each of the process parameters on threshold voltage was determined using analysis of variance (ANOVA). Transistor fabrication was performed by using Silvaco ATHENA module. Silvaco ATLAS module takes care of electrical characterization for the device. These two simulators results were analyzed with Taguchi method to aid in design and optimizing process parameters. Threshold voltage (VTH) results were used as the evaluation parameters. The results show that the VTH value 0.1099 V for NMOS can be achieved respectively, much closer to the ITRS prediction than our previous L9 experiment result. As the conclusion, by utilizing L18 Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.1099 V that is well within ITRS 2003 prediction for 32nm transistor

Original languageEnglish
Title of host publicationAIP Conference Proceedings
Pages543-549
Number of pages7
Volume1482
DOIs
Publication statusPublished - 2012
Event2nd International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012 - Kuala Lumpur
Duration: 12 Jun 201214 Jun 2012

Other

Other2nd International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012
CityKuala Lumpur
Period12/6/1214/6/12

Fingerprint

Taguchi methods
threshold voltage
transistors
implantation
modules
analysis of variance
fabrication
predictions
simulators
CMOS
adjusting
annealing
evaluation

Keywords

  • Compensation Implantation
  • HALO
  • S/D implantation
  • Silicon MOSFET 32nm
  • Taguchi L18
  • Taguchi Method
  • Threshold voltage

ASJC Scopus subject areas

  • Physics and Astronomy(all)

Cite this

Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method. / Elgomati, Husam Ahmed; Yeop Majlis, Burhanuddin; Ahmad, Ibrahim.

AIP Conference Proceedings. Vol. 1482 2012. p. 543-549.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Elgomati, HA, Yeop Majlis, B & Ahmad, I 2012, Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method. in AIP Conference Proceedings. vol. 1482, pp. 543-549, 2nd International Conference on Fundamental and Applied Sciences 2012, ICFAS 2012, Kuala Lumpur, 12/6/12. https://doi.org/10.1063/1.4757531
Elgomati, Husam Ahmed ; Yeop Majlis, Burhanuddin ; Ahmad, Ibrahim. / Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method. AIP Conference Proceedings. Vol. 1482 2012. pp. 543-549
@inproceedings{015ad474e0854b258288d031d2933a28,
title = "Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method",
abstract = "This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilicon thickness and silicide annealing time. The setting of process parameters were determined by Taguchi method L18 experimental design. From there, the level of importance of each of the process parameters on threshold voltage was determined using analysis of variance (ANOVA). Transistor fabrication was performed by using Silvaco ATHENA module. Silvaco ATLAS module takes care of electrical characterization for the device. These two simulators results were analyzed with Taguchi method to aid in design and optimizing process parameters. Threshold voltage (VTH) results were used as the evaluation parameters. The results show that the VTH value 0.1099 V for NMOS can be achieved respectively, much closer to the ITRS prediction than our previous L9 experiment result. As the conclusion, by utilizing L18 Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.1099 V that is well within ITRS 2003 prediction for 32nm transistor",
keywords = "Compensation Implantation, HALO, S/D implantation, Silicon MOSFET 32nm, Taguchi L18, Taguchi Method, Threshold voltage",
author = "Elgomati, {Husam Ahmed} and {Yeop Majlis}, Burhanuddin and Ibrahim Ahmad",
year = "2012",
doi = "10.1063/1.4757531",
language = "English",
isbn = "9780735410947",
volume = "1482",
pages = "543--549",
booktitle = "AIP Conference Proceedings",

}

TY - GEN

T1 - Modeling and optimizing of threshold voltage of 32nm NMOS transistor using L18 orthogonal array Taguchi method

AU - Elgomati, Husam Ahmed

AU - Yeop Majlis, Burhanuddin

AU - Ahmad, Ibrahim

PY - 2012

Y1 - 2012

N2 - This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilicon thickness and silicide annealing time. The setting of process parameters were determined by Taguchi method L18 experimental design. From there, the level of importance of each of the process parameters on threshold voltage was determined using analysis of variance (ANOVA). Transistor fabrication was performed by using Silvaco ATHENA module. Silvaco ATLAS module takes care of electrical characterization for the device. These two simulators results were analyzed with Taguchi method to aid in design and optimizing process parameters. Threshold voltage (VTH) results were used as the evaluation parameters. The results show that the VTH value 0.1099 V for NMOS can be achieved respectively, much closer to the ITRS prediction than our previous L9 experiment result. As the conclusion, by utilizing L18 Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.1099 V that is well within ITRS 2003 prediction for 32nm transistor

AB - This paper describes our investigation of the effect of seven processes' parameters on threshold voltage (VTH) in the fabrication of a 32nm CMOS transistor. The parameters are HALO implantation, S/D Implantation, Compensation implantations, SiO2 thickness, VTH adjustment implantation, polysilicon thickness and silicide annealing time. The setting of process parameters were determined by Taguchi method L18 experimental design. From there, the level of importance of each of the process parameters on threshold voltage was determined using analysis of variance (ANOVA). Transistor fabrication was performed by using Silvaco ATHENA module. Silvaco ATLAS module takes care of electrical characterization for the device. These two simulators results were analyzed with Taguchi method to aid in design and optimizing process parameters. Threshold voltage (VTH) results were used as the evaluation parameters. The results show that the VTH value 0.1099 V for NMOS can be achieved respectively, much closer to the ITRS prediction than our previous L9 experiment result. As the conclusion, by utilizing L18 Taguchi Method shown that process parameters can adjust threshold voltage (VTH) to a stable value of 0.1099 V that is well within ITRS 2003 prediction for 32nm transistor

KW - Compensation Implantation

KW - HALO

KW - S/D implantation

KW - Silicon MOSFET 32nm

KW - Taguchi L18

KW - Taguchi Method

KW - Threshold voltage

UR - http://www.scopus.com/inward/record.url?scp=84874145255&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84874145255&partnerID=8YFLogxK

U2 - 10.1063/1.4757531

DO - 10.1063/1.4757531

M3 - Conference contribution

AN - SCOPUS:84874145255

SN - 9780735410947

VL - 1482

SP - 543

EP - 549

BT - AIP Conference Proceedings

ER -