Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs

A. K. Sharma, Saleem H. Zaidi, S. Lucero, S. R J Brueck, N. E. Islam

Research output: Chapter in Book/Report/Conference proceedingChapter

18 Citations (Scopus)

Abstract

The current conduction process through a nanowire wrap-around-gate, ∼50 nm channel diameter, silicon MOSFET has been investigated and compared with a ∼2 μm wide slab, ∼200 nm thick silicon (SOI) top-only-gate planar MOSFET with otherwise similar doping profiles, gate length and gate oxide thickness. The experimental characteristics of the nanowire and planar MOSFETs were compared with theoretical simulation results based on semi-empirical carrier mobility models. The SOI nanowire MOS devices were fabricated through interferometric lithography in combination with conventional I-line lithography. A significant increase (∼3 x) in current density was observed in the nanowire devices compared to the planar devices. A number of parameters such as carrier confinement, effects of parallel and transverse field-dependent mobilities, and carrier scattering due to Coulomb effects, acoustic phonons, impurity doping profile and surface roughness influences the transport process in the channel regions. The electron mobility in the nanochannel increases to ∼1200cm 2/Vs compared to ∼ 400cm 2/V s for a wide slab planar device of similar channel length. Experiments also show that the application of the channel potential from three sides in the nanowire structure dramatically improves the subthreshold slope characteristics.

Original languageEnglish
Title of host publicationIEE Proceedings: Circuits, Devices and Systems
Pages422-430
Number of pages9
Volume151
Edition5
DOIs
Publication statusPublished - Oct 2004
Externally publishedYes

Fingerprint

Electric field effects
Nanowires
Lithography
Doping (additives)
Silicon
MOS devices
Electron mobility
Carrier mobility
Phonons
Current density
Surface roughness
Acoustics
Scattering
Impurities
Oxides
Experiments

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Sharma, A. K., Zaidi, S. H., Lucero, S., Brueck, S. R. J., & Islam, N. E. (2004). Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs. In IEE Proceedings: Circuits, Devices and Systems (5 ed., Vol. 151, pp. 422-430) https://doi.org/10.1049/ip-cds:20040993

Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs. / Sharma, A. K.; Zaidi, Saleem H.; Lucero, S.; Brueck, S. R J; Islam, N. E.

IEE Proceedings: Circuits, Devices and Systems. Vol. 151 5. ed. 2004. p. 422-430.

Research output: Chapter in Book/Report/Conference proceedingChapter

Sharma, AK, Zaidi, SH, Lucero, S, Brueck, SRJ & Islam, NE 2004, Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs. in IEE Proceedings: Circuits, Devices and Systems. 5 edn, vol. 151, pp. 422-430. https://doi.org/10.1049/ip-cds:20040993
Sharma AK, Zaidi SH, Lucero S, Brueck SRJ, Islam NE. Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs. In IEE Proceedings: Circuits, Devices and Systems. 5 ed. Vol. 151. 2004. p. 422-430 https://doi.org/10.1049/ip-cds:20040993
Sharma, A. K. ; Zaidi, Saleem H. ; Lucero, S. ; Brueck, S. R J ; Islam, N. E. / Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs. IEE Proceedings: Circuits, Devices and Systems. Vol. 151 5. ed. 2004. pp. 422-430
@inbook{0c31092f0f17442589aab11cb1e49ced,
title = "Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs",
abstract = "The current conduction process through a nanowire wrap-around-gate, ∼50 nm channel diameter, silicon MOSFET has been investigated and compared with a ∼2 μm wide slab, ∼200 nm thick silicon (SOI) top-only-gate planar MOSFET with otherwise similar doping profiles, gate length and gate oxide thickness. The experimental characteristics of the nanowire and planar MOSFETs were compared with theoretical simulation results based on semi-empirical carrier mobility models. The SOI nanowire MOS devices were fabricated through interferometric lithography in combination with conventional I-line lithography. A significant increase (∼3 x) in current density was observed in the nanowire devices compared to the planar devices. A number of parameters such as carrier confinement, effects of parallel and transverse field-dependent mobilities, and carrier scattering due to Coulomb effects, acoustic phonons, impurity doping profile and surface roughness influences the transport process in the channel regions. The electron mobility in the nanochannel increases to ∼1200cm 2/Vs compared to ∼ 400cm 2/V s for a wide slab planar device of similar channel length. Experiments also show that the application of the channel potential from three sides in the nanowire structure dramatically improves the subthreshold slope characteristics.",
author = "Sharma, {A. K.} and Zaidi, {Saleem H.} and S. Lucero and Brueck, {S. R J} and Islam, {N. E.}",
year = "2004",
month = "10",
doi = "10.1049/ip-cds:20040993",
language = "English",
volume = "151",
pages = "422--430",
booktitle = "IEE Proceedings: Circuits, Devices and Systems",
edition = "5",

}

TY - CHAP

T1 - Mobility and transverse electric field effects in channel conduction of wrap-around-gate nanowire MOSFETs

AU - Sharma, A. K.

AU - Zaidi, Saleem H.

AU - Lucero, S.

AU - Brueck, S. R J

AU - Islam, N. E.

PY - 2004/10

Y1 - 2004/10

N2 - The current conduction process through a nanowire wrap-around-gate, ∼50 nm channel diameter, silicon MOSFET has been investigated and compared with a ∼2 μm wide slab, ∼200 nm thick silicon (SOI) top-only-gate planar MOSFET with otherwise similar doping profiles, gate length and gate oxide thickness. The experimental characteristics of the nanowire and planar MOSFETs were compared with theoretical simulation results based on semi-empirical carrier mobility models. The SOI nanowire MOS devices were fabricated through interferometric lithography in combination with conventional I-line lithography. A significant increase (∼3 x) in current density was observed in the nanowire devices compared to the planar devices. A number of parameters such as carrier confinement, effects of parallel and transverse field-dependent mobilities, and carrier scattering due to Coulomb effects, acoustic phonons, impurity doping profile and surface roughness influences the transport process in the channel regions. The electron mobility in the nanochannel increases to ∼1200cm 2/Vs compared to ∼ 400cm 2/V s for a wide slab planar device of similar channel length. Experiments also show that the application of the channel potential from three sides in the nanowire structure dramatically improves the subthreshold slope characteristics.

AB - The current conduction process through a nanowire wrap-around-gate, ∼50 nm channel diameter, silicon MOSFET has been investigated and compared with a ∼2 μm wide slab, ∼200 nm thick silicon (SOI) top-only-gate planar MOSFET with otherwise similar doping profiles, gate length and gate oxide thickness. The experimental characteristics of the nanowire and planar MOSFETs were compared with theoretical simulation results based on semi-empirical carrier mobility models. The SOI nanowire MOS devices were fabricated through interferometric lithography in combination with conventional I-line lithography. A significant increase (∼3 x) in current density was observed in the nanowire devices compared to the planar devices. A number of parameters such as carrier confinement, effects of parallel and transverse field-dependent mobilities, and carrier scattering due to Coulomb effects, acoustic phonons, impurity doping profile and surface roughness influences the transport process in the channel regions. The electron mobility in the nanochannel increases to ∼1200cm 2/Vs compared to ∼ 400cm 2/V s for a wide slab planar device of similar channel length. Experiments also show that the application of the channel potential from three sides in the nanowire structure dramatically improves the subthreshold slope characteristics.

UR - http://www.scopus.com/inward/record.url?scp=11144239994&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=11144239994&partnerID=8YFLogxK

U2 - 10.1049/ip-cds:20040993

DO - 10.1049/ip-cds:20040993

M3 - Chapter

AN - SCOPUS:11144239994

VL - 151

SP - 422

EP - 430

BT - IEE Proceedings: Circuits, Devices and Systems

ER -