Low power ROM employing Dynamic Threshold-Voltage MOSFET (DTMOS) technique

M. Mustapa, F. Mohd-Yasin, M. K. Khaw, Md. Mamun Ibne Reaz, A. Kordesch

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper examines the performance of two 128-bit ROM circuits, implemented on Silterra 0.18u CMOS process. The first circuit is built using standard NMOS transistors, runs on 0.9V supply voltage, has gate voltage of 0.45V and consumes 102.07μW power. The second circuit is designed partly using Dynamic Threshold-Voltage MOSFET (DTMOS) transistors with the aim to minimize power consumption. It runs on 0.7V supply and has gate voltage of 0.35V. The DTMOS approach is implemented on the 128-bit ROM core and in the pull up circuit of the column decoder. The latter ROM circuit's power consumption is 38.93μW, 61.86% less than the former, at the expenses of larger die area due to the usage of deep n-well process. The standard and DTMOST circuits have the die areas of 0.139μm2 and 0.235μm2, respectively.

Original languageEnglish
Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
Pages103-107
Number of pages5
DOIs
Publication statusPublished - 2008
Externally publishedYes
Event2008 IEEE International Conference on Semiconductor Electronics, ICSE 2008 - Johor Bahru, Johor
Duration: 25 Nov 200827 Nov 2008

Other

Other2008 IEEE International Conference on Semiconductor Electronics, ICSE 2008
CityJohor Bahru, Johor
Period25/11/0827/11/08

Fingerprint

ROM
Threshold voltage
Networks (circuits)
Transistors
Electric potential
Electric power utilization

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Mustapa, M., Mohd-Yasin, F., Khaw, M. K., Ibne Reaz, M. M., & Kordesch, A. (2008). Low power ROM employing Dynamic Threshold-Voltage MOSFET (DTMOS) technique. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 103-107). [4770286] https://doi.org/10.1109/SMELEC.2008.4770286

Low power ROM employing Dynamic Threshold-Voltage MOSFET (DTMOS) technique. / Mustapa, M.; Mohd-Yasin, F.; Khaw, M. K.; Ibne Reaz, Md. Mamun; Kordesch, A.

IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2008. p. 103-107 4770286.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Mustapa, M, Mohd-Yasin, F, Khaw, MK, Ibne Reaz, MM & Kordesch, A 2008, Low power ROM employing Dynamic Threshold-Voltage MOSFET (DTMOS) technique. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE., 4770286, pp. 103-107, 2008 IEEE International Conference on Semiconductor Electronics, ICSE 2008, Johor Bahru, Johor, 25/11/08. https://doi.org/10.1109/SMELEC.2008.4770286
Mustapa M, Mohd-Yasin F, Khaw MK, Ibne Reaz MM, Kordesch A. Low power ROM employing Dynamic Threshold-Voltage MOSFET (DTMOS) technique. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2008. p. 103-107. 4770286 https://doi.org/10.1109/SMELEC.2008.4770286
Mustapa, M. ; Mohd-Yasin, F. ; Khaw, M. K. ; Ibne Reaz, Md. Mamun ; Kordesch, A. / Low power ROM employing Dynamic Threshold-Voltage MOSFET (DTMOS) technique. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2008. pp. 103-107
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