Low power in nano-scale CMOS memory

Labonnah F. Rahman, F. B. Arith, M. I B Idris, Md. Mamun Ibne Reaz, Mohd Marufuzzaman

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Future technologies required nano-scale CMOS memory to be operating in low power consumption. The minimum operating voltage of the nano-scale CMOS played as a main factor to reduce the power consumption. Consequently, there are some limitations and obstacles to achieve the objective for several design, material and novel structural solutions, which are promising and reliable. In this research, the noticeable limits, possible annexes and applications of CMOS technologies in the nanometer regime is discussed. This paper mainly describes the limitations that conventional MOSFET is faced. In addition, the solutions to low power in nano-scale CMOS memory are presented. Therefore, analysis of the attainable performance and potential restrictions of CMOS technologies from the point of design, material and structural solution techniques are illustrated.

Original languageEnglish
Pages (from-to)297-303
Number of pages7
JournalJournal of Theoretical and Applied Information Technology
Volume61
Issue number2
Publication statusPublished - 2014

Fingerprint

Material Design
Data storage equipment
Power Consumption
Electric power utilization
MOSFET
Structural Design
Voltage
Restriction
Electric potential

Keywords

  • CMOS
  • Low power
  • Memory
  • Nano-scale

ASJC Scopus subject areas

  • Computer Science(all)
  • Theoretical Computer Science

Cite this

Rahman, L. F., Arith, F. B., Idris, M. I. B., Ibne Reaz, M. M., & Marufuzzaman, M. (2014). Low power in nano-scale CMOS memory. Journal of Theoretical and Applied Information Technology, 61(2), 297-303.

Low power in nano-scale CMOS memory. / Rahman, Labonnah F.; Arith, F. B.; Idris, M. I B; Ibne Reaz, Md. Mamun; Marufuzzaman, Mohd.

In: Journal of Theoretical and Applied Information Technology, Vol. 61, No. 2, 2014, p. 297-303.

Research output: Contribution to journalArticle

Rahman, LF, Arith, FB, Idris, MIB, Ibne Reaz, MM & Marufuzzaman, M 2014, 'Low power in nano-scale CMOS memory', Journal of Theoretical and Applied Information Technology, vol. 61, no. 2, pp. 297-303.
Rahman LF, Arith FB, Idris MIB, Ibne Reaz MM, Marufuzzaman M. Low power in nano-scale CMOS memory. Journal of Theoretical and Applied Information Technology. 2014;61(2):297-303.
Rahman, Labonnah F. ; Arith, F. B. ; Idris, M. I B ; Ibne Reaz, Md. Mamun ; Marufuzzaman, Mohd. / Low power in nano-scale CMOS memory. In: Journal of Theoretical and Applied Information Technology. 2014 ; Vol. 61, No. 2. pp. 297-303.
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