Low power high-efficiency shift register using implicit pulse-triggered flip-flop in 130 nm CMOS process for a cryptographic RFID tag

Mohammad Torikul Islam Badal, Md. Mamun Ibne Reaz, Zinah Jalil, Mohammad Arif Sobhan Bhuiyan

Research output: Contribution to journalArticle

3 Citations (Scopus)

Abstract

The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 μm2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

Original languageEnglish
Article number92
JournalElectronics (Switzerland)
Volume5
Issue number4
DOIs
Publication statusPublished - 16 Dec 2016

Fingerprint

Shift registers
Flip flop circuits
Radio frequency identification (RFID)
Transistors
Metals
Sequential circuits
Topology
Sampling
Networks (circuits)
Oxide semiconductors
Tag
Serials
Semiconductors
Radio frequency identification
Logic
High performance
Simulation

Keywords

  • C-element
  • CMOS
  • Flip flop
  • Low power
  • RFID
  • Shift register

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Signal Processing
  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Low power high-efficiency shift register using implicit pulse-triggered flip-flop in 130 nm CMOS process for a cryptographic RFID tag. / Badal, Mohammad Torikul Islam; Ibne Reaz, Md. Mamun; Jalil, Zinah; Bhuiyan, Mohammad Arif Sobhan.

In: Electronics (Switzerland), Vol. 5, No. 4, 92, 16.12.2016.

Research output: Contribution to journalArticle

@article{2e34a547fa6f42008ba86d64bee03889,
title = "Low power high-efficiency shift register using implicit pulse-triggered flip-flop in 130 nm CMOS process for a cryptographic RFID tag",
abstract = "The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 μm2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.",
keywords = "C-element, CMOS, Flip flop, Low power, RFID, Shift register",
author = "Badal, {Mohammad Torikul Islam} and {Ibne Reaz}, {Md. Mamun} and Zinah Jalil and Bhuiyan, {Mohammad Arif Sobhan}",
year = "2016",
month = "12",
day = "16",
doi = "10.3390/electronics5040092",
language = "English",
volume = "5",
journal = "Industry Week",
issn = "0039-0895",
publisher = "Penton Publishing Co.",
number = "4",

}

TY - JOUR

T1 - Low power high-efficiency shift register using implicit pulse-triggered flip-flop in 130 nm CMOS process for a cryptographic RFID tag

AU - Badal, Mohammad Torikul Islam

AU - Ibne Reaz, Md. Mamun

AU - Jalil, Zinah

AU - Bhuiyan, Mohammad Arif Sobhan

PY - 2016/12/16

Y1 - 2016/12/16

N2 - The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 μm2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

AB - The shift register is a type of sequential logic circuit which is mostly used for storing digital data or the transferring of data in the form of binary numbers in radio frequency identification (RFID) applications to improve the security of the system. A power-efficient shift register utilizing a new flip-flop with an implicit pulse-triggered structure is presented in this article. The proposed flip-flop has features of high performance and low power. It is composed of a sampling circuit implemented by five transistors, a C-element for rise and fall paths, and a keeper stage. The speed is enhanced by executing four clocked transistors together with a transition condition technique. The simulation result confirms that the proposed topology consumes the lowest amounts of power of 30.1997 and 22.7071 nW for parallel in –parallel out (PIPO) and serial in –serial out (SISO) shift register respectively covering 22 μm2 chip area. The overall design consist of only 16 transistors and is simulated in 130 nm complementary-metal-oxide-semiconductor (CMOS) technology with a 1.2 V power supply.

KW - C-element

KW - CMOS

KW - Flip flop

KW - Low power

KW - RFID

KW - Shift register

UR - http://www.scopus.com/inward/record.url?scp=85016036000&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85016036000&partnerID=8YFLogxK

U2 - 10.3390/electronics5040092

DO - 10.3390/electronics5040092

M3 - Article

AN - SCOPUS:85016036000

VL - 5

JO - Industry Week

JF - Industry Week

SN - 0039-0895

IS - 4

M1 - 92

ER -