Low power delay locked-loop using 0.13μm CMOS technology

Torikul Islam Badal, Pouya Maroofee, Mohammad Arif Sobhan Bhuiyan, Labonnah F. Rahman, Md. Mamun Ibne Reaz, Mohammad Abdul Mukit

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

In this paper, a low power delay locked-loop with modified voltage-controlled delay cell (VCDC) is proposed. This modified VCDC is designed by using Mentor Graphic CEDEC design kit and Silterra 0.13μm process technology. Thus, the DLL with proposed VCDC able to obtained low power dissipation which is 921.57μW and occupied very smaller area which is 0.03mm2.

Original languageEnglish
Title of host publication2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages176-179
Number of pages4
ISBN (Electronic)9781509028894
DOIs
Publication statusPublished - 27 Mar 2017
Event2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 - Putrajaya, Malaysia
Duration: 14 Nov 201616 Nov 2016

Other

Other2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016
CountryMalaysia
CityPutrajaya
Period14/11/1616/11/16

Fingerprint

CMOS
Electric potential
electric potential
cells
kits
Energy dissipation
dissipation

Keywords

  • Area
  • Delay locked loop (DLL)
  • Low power
  • Power dissipation
  • Voltage-controlled delay cell (VCDC)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Biomedical Engineering
  • Control and Systems Engineering
  • Hardware and Architecture
  • Computer Networks and Communications
  • Instrumentation

Cite this

Badal, T. I., Maroofee, P., Bhuiyan, M. A. S., Rahman, L. F., Ibne Reaz, M. M., & Mukit, M. A. (2017). Low power delay locked-loop using 0.13μm CMOS technology. In 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016 (pp. 176-179). [7888033] Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICAEES.2016.7888033

Low power delay locked-loop using 0.13μm CMOS technology. / Badal, Torikul Islam; Maroofee, Pouya; Bhuiyan, Mohammad Arif Sobhan; Rahman, Labonnah F.; Ibne Reaz, Md. Mamun; Mukit, Mohammad Abdul.

2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc., 2017. p. 176-179 7888033.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Badal, TI, Maroofee, P, Bhuiyan, MAS, Rahman, LF, Ibne Reaz, MM & Mukit, MA 2017, Low power delay locked-loop using 0.13μm CMOS technology. in 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016., 7888033, Institute of Electrical and Electronics Engineers Inc., pp. 176-179, 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016, Putrajaya, Malaysia, 14/11/16. https://doi.org/10.1109/ICAEES.2016.7888033
Badal TI, Maroofee P, Bhuiyan MAS, Rahman LF, Ibne Reaz MM, Mukit MA. Low power delay locked-loop using 0.13μm CMOS technology. In 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc. 2017. p. 176-179. 7888033 https://doi.org/10.1109/ICAEES.2016.7888033
Badal, Torikul Islam ; Maroofee, Pouya ; Bhuiyan, Mohammad Arif Sobhan ; Rahman, Labonnah F. ; Ibne Reaz, Md. Mamun ; Mukit, Mohammad Abdul. / Low power delay locked-loop using 0.13μm CMOS technology. 2016 International Conference on Advances in Electrical, Electronic and Systems Engineering, ICAEES 2016. Institute of Electrical and Electronics Engineers Inc., 2017. pp. 176-179
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AU - Ibne Reaz, Md. Mamun

AU - Mukit, Mohammad Abdul

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