Low dropout voltage regulator using 130 nm CMOS technology

Mohammad Marufuzzaman, Md. Mamun Ibne Reaz, Labonnah Farzana Rahman, Norhaida Binti Mustafa, Araf Farayez

Research output: Contribution to journalArticle

Abstract

In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of 703 µm2, ensuring that the proposed circuit is suitable for low-power applications.

Original languageEnglish
Pages (from-to)257-260
Number of pages4
JournalTransactions on Electrical and Electronic Materials
Volume18
Issue number5
DOIs
Publication statusPublished - 25 Oct 2017

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Voltage regulators
Electric potential
Networks (circuits)
Operational amplifiers
Energy dissipation
Transistors

Keywords

  • CMOS
  • LDo regulator
  • Low power
  • Operational transconductance amplifier

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Low dropout voltage regulator using 130 nm CMOS technology. / Marufuzzaman, Mohammad; Ibne Reaz, Md. Mamun; Rahman, Labonnah Farzana; Mustafa, Norhaida Binti; Farayez, Araf.

In: Transactions on Electrical and Electronic Materials, Vol. 18, No. 5, 25.10.2017, p. 257-260.

Research output: Contribution to journalArticle

Marufuzzaman, Mohammad ; Ibne Reaz, Md. Mamun ; Rahman, Labonnah Farzana ; Mustafa, Norhaida Binti ; Farayez, Araf. / Low dropout voltage regulator using 130 nm CMOS technology. In: Transactions on Electrical and Electronic Materials. 2017 ; Vol. 18, No. 5. pp. 257-260.
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