LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage

Syed Zahidul Islam, Mohd Alauddin Mohd Ali

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

This paper presents a low hardware overhead scan- based test pattern generator (TPG) that can reduce switching activity in circuit under test (CUT) during test and also achieve very high fault coverage with reasonable lengths of test sequences. The proposed TPG is comprised of two TPGs: Seed selected Random Test Pattern Generator (RTPG) and 3-weight Weighted Random Built-in-Self Test (WRBIST). Test pattern generated by seed selected RTPG detect easy-to-detect faults and test pattern generated by 3-weight WRBIST detect hard faults that remain undetected after seed selected RTPG patterns are applied. Experimental results show that the proposed TPG schemes can attain 100% fault coverage for all benchmark circuits with drastically reduced test sequence lengths. This reduction in test sequence length achieved at low hardware cost even for benchmark circuits that have large number of scan inputs.

Original languageEnglish
Title of host publicationIEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
Pages1755-1758
Number of pages4
DOIs
Publication statusPublished - 2008
Externally publishedYes
EventAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems - Macao
Duration: 30 Nov 20083 Dec 2008

Other

OtherAPCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems
CityMacao
Period30/11/083/12/08

Fingerprint

Seed
Energy dissipation
Built-in self test
Networks (circuits)
Hardware
Costs

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

Cite this

Islam, S. Z., & Ali, M. A. M. (2008). LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS (pp. 1755-1758). [4746380] https://doi.org/10.1109/APCCAS.2008.4746380

LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage. / Islam, Syed Zahidul; Ali, Mohd Alauddin Mohd.

IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2008. p. 1755-1758 4746380.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Islam, SZ & Ali, MAM 2008, LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage. in IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS., 4746380, pp. 1755-1758, APCCAS 2008 - 2008 IEEE Asia Pacific Conference on Circuits and Systems, Macao, 30/11/08. https://doi.org/10.1109/APCCAS.2008.4746380
Islam SZ, Ali MAM. LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage. In IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2008. p. 1755-1758. 4746380 https://doi.org/10.1109/APCCAS.2008.4746380
Islam, Syed Zahidul ; Ali, Mohd Alauddin Mohd. / LFSR based hybrid pattern scheme achieving low power dissipation and high fault coverage. IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS. 2008. pp. 1755-1758
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