LFSR based fast seed selection technique reducing test time of I DDQ testing

Syed Zahidul Islam, Razali Bin Jidin, Mohd Alauddin Mohd Ali

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    1 Citation (Scopus)

    Abstract

    This paper proposed IDDQ testing of combinational circuit using Linear Feedback Shift Register (LFSR) based fast seed selection technique. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing. To reduce test time of IDDQ testing, bit-flipping technique is integrated with LFSR to reduce lower to higher (L to H) switching activities for combinational circuits. Experimental results for ISCAS'85 and ISCAS'89 benchmark circuits show the effectiveness (7% improvement) of the technique for reducing testing time delay.

    Original languageEnglish
    Title of host publication2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings
    Pages362-364
    Number of pages3
    Volume1
    DOIs
    Publication statusPublished - 16 Dec 2009
    Event2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Kuala Lumpur
    Duration: 4 Oct 20096 Oct 2009

    Other

    Other2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009
    CityKuala Lumpur
    Period4/10/096/10/09

    Fingerprint

    Shift registers
    Seed
    Feedback
    Testing
    Combinatorial circuits
    Networks (circuits)
    Time delay

    Keywords

    • Bridging fault
    • I
    • LFSR

    ASJC Scopus subject areas

    • Computer Networks and Communications
    • Computer Science Applications
    • Hardware and Architecture
    • Electrical and Electronic Engineering

    Cite this

    Islam, S. Z., Jidin, R. B., & Ali, M. A. M. (2009). LFSR based fast seed selection technique reducing test time of I DDQ testing. In 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings (Vol. 1, pp. 362-364). [5356430] https://doi.org/10.1109/ISIEA.2009.5356430

    LFSR based fast seed selection technique reducing test time of I DDQ testing. / Islam, Syed Zahidul; Jidin, Razali Bin; Ali, Mohd Alauddin Mohd.

    2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings. Vol. 1 2009. p. 362-364 5356430.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Islam, SZ, Jidin, RB & Ali, MAM 2009, LFSR based fast seed selection technique reducing test time of I DDQ testing. in 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings. vol. 1, 5356430, pp. 362-364, 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009, Kuala Lumpur, 4/10/09. https://doi.org/10.1109/ISIEA.2009.5356430
    Islam SZ, Jidin RB, Ali MAM. LFSR based fast seed selection technique reducing test time of I DDQ testing. In 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings. Vol. 1. 2009. p. 362-364. 5356430 https://doi.org/10.1109/ISIEA.2009.5356430
    Islam, Syed Zahidul ; Jidin, Razali Bin ; Ali, Mohd Alauddin Mohd. / LFSR based fast seed selection technique reducing test time of I DDQ testing. 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings. Vol. 1 2009. pp. 362-364
    @inproceedings{ebce4f219cfb4f6ba8cb10b2e66669cb,
    title = "LFSR based fast seed selection technique reducing test time of I DDQ testing",
    abstract = "This paper proposed IDDQ testing of combinational circuit using Linear Feedback Shift Register (LFSR) based fast seed selection technique. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing. To reduce test time of IDDQ testing, bit-flipping technique is integrated with LFSR to reduce lower to higher (L to H) switching activities for combinational circuits. Experimental results for ISCAS'85 and ISCAS'89 benchmark circuits show the effectiveness (7{\%} improvement) of the technique for reducing testing time delay.",
    keywords = "Bridging fault, I, LFSR",
    author = "Islam, {Syed Zahidul} and Jidin, {Razali Bin} and Ali, {Mohd Alauddin Mohd}",
    year = "2009",
    month = "12",
    day = "16",
    doi = "10.1109/ISIEA.2009.5356430",
    language = "English",
    isbn = "9781424446827",
    volume = "1",
    pages = "362--364",
    booktitle = "2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings",

    }

    TY - GEN

    T1 - LFSR based fast seed selection technique reducing test time of I DDQ testing

    AU - Islam, Syed Zahidul

    AU - Jidin, Razali Bin

    AU - Ali, Mohd Alauddin Mohd

    PY - 2009/12/16

    Y1 - 2009/12/16

    N2 - This paper proposed IDDQ testing of combinational circuit using Linear Feedback Shift Register (LFSR) based fast seed selection technique. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing. To reduce test time of IDDQ testing, bit-flipping technique is integrated with LFSR to reduce lower to higher (L to H) switching activities for combinational circuits. Experimental results for ISCAS'85 and ISCAS'89 benchmark circuits show the effectiveness (7% improvement) of the technique for reducing testing time delay.

    AB - This paper proposed IDDQ testing of combinational circuit using Linear Feedback Shift Register (LFSR) based fast seed selection technique. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing. To reduce test time of IDDQ testing, bit-flipping technique is integrated with LFSR to reduce lower to higher (L to H) switching activities for combinational circuits. Experimental results for ISCAS'85 and ISCAS'89 benchmark circuits show the effectiveness (7% improvement) of the technique for reducing testing time delay.

    KW - Bridging fault

    KW - I

    KW - LFSR

    UR - http://www.scopus.com/inward/record.url?scp=76449108054&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=76449108054&partnerID=8YFLogxK

    U2 - 10.1109/ISIEA.2009.5356430

    DO - 10.1109/ISIEA.2009.5356430

    M3 - Conference contribution

    SN - 9781424446827

    VL - 1

    SP - 362

    EP - 364

    BT - 2009 IEEE Symposium on Industrial Electronics and Applications, ISIEA 2009 - Proceedings

    ER -