Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device

Norani Binti Atan, Ibrahim Bin Ahmad, Burhanuddin Yeop Majlis, Izzati Binti Ahmad Fauzi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

The process parameters are very crucial factor in the development of transistors. There are many process parameters that influenced in the development of the transistors. In this research, we investigate the effects of the process parameters variation on response characteristics such as threshold voltage (VTH) and sub-threshold leakage current (IOFF) in 18nm NMOS device. The technique to identify semiconductor process parameters whose variability would impact most on the device characteristic is realized through the process by using Taguchi robust design method. This paper presents the process parameters that influenced in threshold voltage (VTH) and sub-threshold leakage current (IOFF) which includes the Halo Implantation, Compensation Implantation, Adjustment Threshold voltage Implantation and Source/Drain Implantation. The design, fabrication and characterization of 18nm HfO2/TiSi2 NMOS device is simulated and performed via a tool called Virtual Wafer Fabrication (VWF) Silvaco TCAD Tool known as ATHENA and ATLAS simulators. These two simulators were combined with Taguchi L9 Orthogonal method to aid in the design and the optimization of the process parameters to achieve the optimum average of threshold voltage (VTH) and sub-threshold leakage current, (IOFF) in 18nm device. Results from this research were obtained; where Halo Implantation dose was identified as one of the process parameter that has the strongest effect on the response characteristics. Whereby the Compensation Implantation dose was identified as an adjustment factor to get the nominal values of threshold voltage VTH, and sub-threshold leakage current, IOFF for 18nm NMOS devices equal to 0.302849 volts and 1.9123×10-16 A/μm respectively. The design values are referred to ITRS 2011 prediction.

Original languageEnglish
Title of host publicationNational Physics Conference 2014, PERFIK 2014
PublisherAmerican Institute of Physics Inc.
Volume1657
ISBN (Electronic)9780735412996
DOIs
Publication statusPublished - 24 Apr 2015
EventNational Physics Conference 2014, PERFIK 2014 - Kuala Lumpur, Malaysia
Duration: 18 Nov 201419 Nov 2014

Other

OtherNational Physics Conference 2014, PERFIK 2014
CountryMalaysia
CityKuala Lumpur
Period18/11/1419/11/14

Fingerprint

threshold voltage
leakage
implantation
thresholds
simulators
halos
transistors
adjusting
dosage
fabrication
design optimization
wafers
optimization
predictions
approximation

Keywords

  • 18nm NMOS
  • HfO-High-K dielectric
  • Silvaco Software
  • Taguchi Method
  • TiSi-Metal Gate Transistor

ASJC Scopus subject areas

  • Physics and Astronomy(all)

Cite this

Atan, N. B., Ahmad, I. B., Yeop Majlis, B., & Fauzi, I. B. A. (2015). Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device. In National Physics Conference 2014, PERFIK 2014 (Vol. 1657). [110002] American Institute of Physics Inc.. https://doi.org/10.1063/1.4915221

Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device. / Atan, Norani Binti; Ahmad, Ibrahim Bin; Yeop Majlis, Burhanuddin; Fauzi, Izzati Binti Ahmad.

National Physics Conference 2014, PERFIK 2014. Vol. 1657 American Institute of Physics Inc., 2015. 110002.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Atan, NB, Ahmad, IB, Yeop Majlis, B & Fauzi, IBA 2015, Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device. in National Physics Conference 2014, PERFIK 2014. vol. 1657, 110002, American Institute of Physics Inc., National Physics Conference 2014, PERFIK 2014, Kuala Lumpur, Malaysia, 18/11/14. https://doi.org/10.1063/1.4915221
Atan NB, Ahmad IB, Yeop Majlis B, Fauzi IBA. Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device. In National Physics Conference 2014, PERFIK 2014. Vol. 1657. American Institute of Physics Inc. 2015. 110002 https://doi.org/10.1063/1.4915221
Atan, Norani Binti ; Ahmad, Ibrahim Bin ; Yeop Majlis, Burhanuddin ; Fauzi, Izzati Binti Ahmad. / Influence of process parameters on threshold voltage and leakage current in 18nm NMOS device. National Physics Conference 2014, PERFIK 2014. Vol. 1657 American Institute of Physics Inc., 2015.
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abstract = "The process parameters are very crucial factor in the development of transistors. There are many process parameters that influenced in the development of the transistors. In this research, we investigate the effects of the process parameters variation on response characteristics such as threshold voltage (VTH) and sub-threshold leakage current (IOFF) in 18nm NMOS device. The technique to identify semiconductor process parameters whose variability would impact most on the device characteristic is realized through the process by using Taguchi robust design method. This paper presents the process parameters that influenced in threshold voltage (VTH) and sub-threshold leakage current (IOFF) which includes the Halo Implantation, Compensation Implantation, Adjustment Threshold voltage Implantation and Source/Drain Implantation. The design, fabrication and characterization of 18nm HfO2/TiSi2 NMOS device is simulated and performed via a tool called Virtual Wafer Fabrication (VWF) Silvaco TCAD Tool known as ATHENA and ATLAS simulators. These two simulators were combined with Taguchi L9 Orthogonal method to aid in the design and the optimization of the process parameters to achieve the optimum average of threshold voltage (VTH) and sub-threshold leakage current, (IOFF) in 18nm device. Results from this research were obtained; where Halo Implantation dose was identified as one of the process parameter that has the strongest effect on the response characteristics. Whereby the Compensation Implantation dose was identified as an adjustment factor to get the nominal values of threshold voltage VTH, and sub-threshold leakage current, IOFF for 18nm NMOS devices equal to 0.302849 volts and 1.9123×10-16 A/μm respectively. The design values are referred to ITRS 2011 prediction.",
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