Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits

Sawal Hamid Md Ali, Ke Li, Reuben Wilcock, Peter Wilson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A new approach in hierarchical optimisation is presented which is capable of optimising both the performance and yield of an analogue design. Performance and yield trade offs are analysed using a combination of multi-objective evolutionary algorithms and Monte Carlo simulations. A behavioural model that combines the performance and variation for a given circuit topology is developed which can be used to optimise the system level structure. The approach enables top-down system optimisation, not only for performance but also for yield. The model has been developed in Verilog-A and tested extensively with practical designs using the Spectre simulator. A performance and variation model of a 5 stage voltage controlled ring oscillator has been developed and a PLL design is used to demonstrate hierarchical optimisation at the system level. The results have been verified with transistor level simulations and suggest that an accurate performance and yield prediction can be achieved with the proposed algorithm.

Original languageEnglish
Title of host publicationProceedings -Design, Automation and Test in Europe, DATE
Pages712-717
Number of pages6
Publication statusPublished - 2009
Externally publishedYes
Event2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09 - Nice
Duration: 20 Apr 200924 Apr 2009

Other

Other2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09
CityNice
Period20/4/0924/4/09

Fingerprint

Computer hardware description languages
Electric network topology
Phase locked loops
Evolutionary algorithms
Transistors
Simulators
Electric potential
Analog integrated circuits
Monte Carlo simulation

ASJC Scopus subject areas

  • Engineering(all)

Cite this

Md Ali, S. H., Li, K., Wilcock, R., & Wilson, P. (2009). Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits. In Proceedings -Design, Automation and Test in Europe, DATE (pp. 712-717). [5090757]

Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits. / Md Ali, Sawal Hamid; Li, Ke; Wilcock, Reuben; Wilson, Peter.

Proceedings -Design, Automation and Test in Europe, DATE. 2009. p. 712-717 5090757.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Md Ali, SH, Li, K, Wilcock, R & Wilson, P 2009, Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits. in Proceedings -Design, Automation and Test in Europe, DATE., 5090757, pp. 712-717, 2009 Design, Automation and Test in Europe Conference and Exhibition, DATE '09, Nice, 20/4/09.
Md Ali SH, Li K, Wilcock R, Wilson P. Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits. In Proceedings -Design, Automation and Test in Europe, DATE. 2009. p. 712-717. 5090757
Md Ali, Sawal Hamid ; Li, Ke ; Wilcock, Reuben ; Wilson, Peter. / Improved performance and variation modelling for hierarchical-based optimisation of analogue integrated circuits. Proceedings -Design, Automation and Test in Europe, DATE. 2009. pp. 712-717
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