Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system

S. Z. Islam, M. A M Ali

    Research output: Contribution to journalArticle

    Abstract

    The optimisation of combined built-in self-test (BIST) and automatic test equipment (ATE) is desirable for complex fabricated chip testing to meet the high fault coverage while preserving acceptable costs. The fault coverage of BIST and ATE plays a significant role, because it can affect the area overhead in BIST and the test time in BIST/ATE. In this paper, a test circuit system (TCS) employing the hybrid technique (combined BIST/ATE) of test pattern generation is presented. The very large scale integration (VLSI) circuit testing features of the hybrid technique overcome the requirements for expensive ATE, as well as extra silicon area in BIST applications. The extendable input/output bus and IDDQ features for the TCS are also shown to enhance the testing capacity corresponding to recent VLSI circuit and system-on-chip requirements.

    Original languageEnglish
    Pages (from-to)73-82
    Number of pages10
    JournalAustralian Journal of Electrical and Electronics Engineering
    Volume7
    Issue number1
    Publication statusPublished - 2010

    Fingerprint

    Built-in self test
    VLSI circuits
    Networks (circuits)
    Testing
    Costs
    Silicon

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

    Cite this

    Implementation of low-cost reconfigurable external mixed-signal VLSI circuit testing system. / Islam, S. Z.; Ali, M. A M.

    In: Australian Journal of Electrical and Electronics Engineering, Vol. 7, No. 1, 2010, p. 73-82.

    Research output: Contribution to journalArticle

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