Implementation of a high speed Fast Fourier Transform VLSI chip

Salina Abdul Samad, A. Ragoub, M. Othman, Z. A M Shariff

Research output: Contribution to journalArticle

8 Citations (Scopus)

Abstract

Very high speed processing of radar signals has led to the requirement of very high speed conversion of signals from the time domain to the frequency domain. In this paper we discuss the implementation of an FFT chip based on the proposed digit slicing architecture. The paper begins with a discussion of the digit slicing technique. This is followed by discussions on the basic building blocks of the digit slicing FFT and implementation of a prototype digit slicing FFT using DSP station. The paper is concluded by comparing the speed and other properties of the unsliced FFT and digit slicing FFT architectures.

Original languageEnglish
Pages (from-to)881-887
Number of pages7
JournalMicroelectronics Journal
Volume29
Issue number11
Publication statusPublished - Nov 1998
Externally publishedYes

Fingerprint

slicing
digits
fast Fourier transformations
very large scale integration
Fast Fourier transforms
chips
high speed
radar
Radar
stations
prototypes
requirements
Processing

ASJC Scopus subject areas

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

Cite this

Abdul Samad, S., Ragoub, A., Othman, M., & Shariff, Z. A. M. (1998). Implementation of a high speed Fast Fourier Transform VLSI chip. Microelectronics Journal, 29(11), 881-887.

Implementation of a high speed Fast Fourier Transform VLSI chip. / Abdul Samad, Salina; Ragoub, A.; Othman, M.; Shariff, Z. A M.

In: Microelectronics Journal, Vol. 29, No. 11, 11.1998, p. 881-887.

Research output: Contribution to journalArticle

Abdul Samad, S, Ragoub, A, Othman, M & Shariff, ZAM 1998, 'Implementation of a high speed Fast Fourier Transform VLSI chip', Microelectronics Journal, vol. 29, no. 11, pp. 881-887.
Abdul Samad, Salina ; Ragoub, A. ; Othman, M. ; Shariff, Z. A M. / Implementation of a high speed Fast Fourier Transform VLSI chip. In: Microelectronics Journal. 1998 ; Vol. 29, No. 11. pp. 881-887.
@article{78067dbe5afe4e509ccef208fb963d45,
title = "Implementation of a high speed Fast Fourier Transform VLSI chip",
abstract = "Very high speed processing of radar signals has led to the requirement of very high speed conversion of signals from the time domain to the frequency domain. In this paper we discuss the implementation of an FFT chip based on the proposed digit slicing architecture. The paper begins with a discussion of the digit slicing technique. This is followed by discussions on the basic building blocks of the digit slicing FFT and implementation of a prototype digit slicing FFT using DSP station. The paper is concluded by comparing the speed and other properties of the unsliced FFT and digit slicing FFT architectures.",
author = "{Abdul Samad}, Salina and A. Ragoub and M. Othman and Shariff, {Z. A M}",
year = "1998",
month = "11",
language = "English",
volume = "29",
pages = "881--887",
journal = "Microelectronics",
issn = "0026-2692",
publisher = "Elsevier Limited",
number = "11",

}

TY - JOUR

T1 - Implementation of a high speed Fast Fourier Transform VLSI chip

AU - Abdul Samad, Salina

AU - Ragoub, A.

AU - Othman, M.

AU - Shariff, Z. A M

PY - 1998/11

Y1 - 1998/11

N2 - Very high speed processing of radar signals has led to the requirement of very high speed conversion of signals from the time domain to the frequency domain. In this paper we discuss the implementation of an FFT chip based on the proposed digit slicing architecture. The paper begins with a discussion of the digit slicing technique. This is followed by discussions on the basic building blocks of the digit slicing FFT and implementation of a prototype digit slicing FFT using DSP station. The paper is concluded by comparing the speed and other properties of the unsliced FFT and digit slicing FFT architectures.

AB - Very high speed processing of radar signals has led to the requirement of very high speed conversion of signals from the time domain to the frequency domain. In this paper we discuss the implementation of an FFT chip based on the proposed digit slicing architecture. The paper begins with a discussion of the digit slicing technique. This is followed by discussions on the basic building blocks of the digit slicing FFT and implementation of a prototype digit slicing FFT using DSP station. The paper is concluded by comparing the speed and other properties of the unsliced FFT and digit slicing FFT architectures.

UR - http://www.scopus.com/inward/record.url?scp=0032210565&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0032210565&partnerID=8YFLogxK

M3 - Article

VL - 29

SP - 881

EP - 887

JO - Microelectronics

JF - Microelectronics

SN - 0026-2692

IS - 11

ER -