Implementation of a 32-bit high speed phase accumulator for direct digital frequency synthesizer

Salah Hasan Ibrahim, Sawal Hamid Md Ali, Md. Shabiul Islam

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This study presents 32-bit Phase Accumulator (PA) design, using1 the pipelining stages with modified Brent-kung (BK) adder. In this design, clock pulse division technique applied to reduce the number of the registers and thus reduce the power consumption. The new architecture of the 32-bit Phase accumulator with modified BK adder and clock pulse division technique, reduce the number of PA registers from 119-81 registers correspond to about 32% reduction. The comparing results of the proposed PA designs with the other designs, using the ALTERA software (Quartus 2 Cyclone 3) reveals that the PA designs with modified BKrun about 27% faster and less delay compared with the previous works, as well as with the lowest number of registers and logic cells.

Original languageEnglish
Pages (from-to)118-124
Number of pages7
JournalAsian Journal of Scientific Research
Volume7
Issue number1
DOIs
Publication statusPublished - 2014

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Frequency synthesizers
Adders
Clocks
Electric power utilization

Keywords

  • Brent-kung adder
  • Direct digital frequency synthesizer
  • Phase accumulator

ASJC Scopus subject areas

  • General

Cite this

Implementation of a 32-bit high speed phase accumulator for direct digital frequency synthesizer. / Ibrahim, Salah Hasan; Md Ali, Sawal Hamid; Islam, Md. Shabiul.

In: Asian Journal of Scientific Research, Vol. 7, No. 1, 2014, p. 118-124.

Research output: Contribution to journalArticle

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