Abstract
This paper presents a high speed direct digital frequency synthesizer (DDFS) using pipelining phase accumulator (PA) with a modified parallel prefix adder based on Brent-Kung (BK) adder. The proposed 32-bit phase accumulator design consists of four pipeline stages, with 8-bit Registers and modifying 8-bit Brent-Kung adder in each stage with carries ripple between the stages. The proposed architecture with modifying 8-bit Brent-Kung adder has been implemented on Cyclone III FPGA kit. A comparison with conventional phase accumulator that using ripple carry adder (RCA) has been made and the results shown that the proposed architecture performs 24.9% faster than the conventional phase accumulator.
| Original language | English |
|---|---|
| Title of host publication | 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings |
| Pages | 547-550 |
| Number of pages | 4 |
| DOIs | |
| Publication status | Published - 2012 |
| Event | 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Kuala Lumpur Duration: 19 Sep 2012 → 21 Sep 2012 |
Other
| Other | 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 |
|---|---|
| City | Kuala Lumpur |
| Period | 19/9/12 → 21/9/12 |
Fingerprint
Keywords
- Brent-Kung adder (BK)
- direct digital frequency synthesizer (DDFS)
- phase accumulator (PA)
- ripple carry adder (RCA)
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
Cite this
High speed direct digital frequency synthesizer with pipelining phase accumulator based on Brent-Kung adder. / Ibrahim, Salah Hasan; Md Ali, Sawal Hamid; Islam, Md. Shabiul.
2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings. 2012. p. 547-550 6417205.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
}
TY - GEN
T1 - High speed direct digital frequency synthesizer with pipelining phase accumulator based on Brent-Kung adder
AU - Ibrahim, Salah Hasan
AU - Md Ali, Sawal Hamid
AU - Islam, Md. Shabiul
PY - 2012
Y1 - 2012
N2 - This paper presents a high speed direct digital frequency synthesizer (DDFS) using pipelining phase accumulator (PA) with a modified parallel prefix adder based on Brent-Kung (BK) adder. The proposed 32-bit phase accumulator design consists of four pipeline stages, with 8-bit Registers and modifying 8-bit Brent-Kung adder in each stage with carries ripple between the stages. The proposed architecture with modifying 8-bit Brent-Kung adder has been implemented on Cyclone III FPGA kit. A comparison with conventional phase accumulator that using ripple carry adder (RCA) has been made and the results shown that the proposed architecture performs 24.9% faster than the conventional phase accumulator.
AB - This paper presents a high speed direct digital frequency synthesizer (DDFS) using pipelining phase accumulator (PA) with a modified parallel prefix adder based on Brent-Kung (BK) adder. The proposed 32-bit phase accumulator design consists of four pipeline stages, with 8-bit Registers and modifying 8-bit Brent-Kung adder in each stage with carries ripple between the stages. The proposed architecture with modifying 8-bit Brent-Kung adder has been implemented on Cyclone III FPGA kit. A comparison with conventional phase accumulator that using ripple carry adder (RCA) has been made and the results shown that the proposed architecture performs 24.9% faster than the conventional phase accumulator.
KW - Brent-Kung adder (BK)
KW - direct digital frequency synthesizer (DDFS)
KW - phase accumulator (PA)
KW - ripple carry adder (RCA)
UR - http://www.scopus.com/inward/record.url?scp=84874136964&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84874136964&partnerID=8YFLogxK
U2 - 10.1109/SMElec.2012.6417205
DO - 10.1109/SMElec.2012.6417205
M3 - Conference contribution
SN - 9781467323963
SP - 547
EP - 550
BT - 2012 10th IEEE International Conference on Semiconductor Electronics, ICSE 2012 - Proceedings
ER -