High-resolution time to digital converter in 0.13 μm CMOS process for RFID phase locked loop

Md T.I. Badal, Md J. Alam, Mamun B.I. Reaz, Mohammad A.S. Bhuiyan, Nahid A. Jahan

Research output: Contribution to journalArticle

Abstract

Time to Digital Converter (TDC) has become an attractive replacement of the traditional phase/frequency detector and charge pump with the appearance of digitally intensive All-Digital Phase-Locked-Loop (ADPLL) in deep submicron Complementary Metal-Oxide Semiconductor (CMOS). The performance of Radio Frequency Identification (RFID) ADPLL is limited by the TDC time resolution because it contributes to the in-band phase noise. The available TDC design consumes more power and also difficult to implement in ADPLL because of its complex circuitry. In this article, a simple TDC architecture, based on modified current starved delay element and D flip-flop, has been proposed for RFID ADPLL, which is implemented and tested in TSMC 0.13 μm CMOS process. The proposed TDC circuit achieves 1.31 ps resolution and consumes an average power of 0.061 μW only with 1.8 V power supply. The designed TDC will be suitable to be used in ADPLL frequency synthesizer for RFID applications, high-speed data transmission, automotive solutions etc.

Original languageEnglish
Pages (from-to)1776-1788
Number of pages13
JournalJournal of Engineering Science and Technology
Volume14
Issue number4
Publication statusPublished - 1 Jan 2019

Fingerprint

Phase locked loops
Radio frequency identification (RFID)
Metals
Frequency synthesizers
Flip flop circuits
Phase noise
Data communication systems
Oxide semiconductors
Pumps
Detectors
Networks (circuits)

Keywords

  • All-digital phase-locked loop (ADPLL)
  • CMOS
  • Delay-line TDC (DL-TDC)
  • TDC

ASJC Scopus subject areas

  • Engineering(all)

Cite this

High-resolution time to digital converter in 0.13 μm CMOS process for RFID phase locked loop. / Badal, Md T.I.; Alam, Md J.; Reaz, Mamun B.I.; Bhuiyan, Mohammad A.S.; Jahan, Nahid A.

In: Journal of Engineering Science and Technology, Vol. 14, No. 4, 01.01.2019, p. 1776-1788.

Research output: Contribution to journalArticle

Badal, Md T.I. ; Alam, Md J. ; Reaz, Mamun B.I. ; Bhuiyan, Mohammad A.S. ; Jahan, Nahid A. / High-resolution time to digital converter in 0.13 μm CMOS process for RFID phase locked loop. In: Journal of Engineering Science and Technology. 2019 ; Vol. 14, No. 4. pp. 1776-1788.
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