High performance parallel multiplier using Wallace-Booth algorithm

[No Value] Lakshmanan, Masuri Othman, Mohamad Alauddin Mohamad

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    14 Citations (Scopus)

    Abstract

    This paper presents an efficient implementation of a VLSI high speed parallel multiplier using the Radix-4 modified Booth algorithm and the Wallace Tree structure .The design is structured for a n × m in multiplication where n can reach up to 126 bits. The Wallace Tree structure serves to compress the partial product term by a ratio of 3:2 [1] .To enhance the speed of operation, carry-look-ahead(CLA) adders are used which is independent on the number of bits of the two operands[2]. An efficient VHDL code was written and successfully simulated and synthesised using Altera's MaxplusII(10.0) and ModeISim3.4 CAD tools.

    Original languageEnglish
    Title of host publicationIEEE International Conference on Semiconductor Electronics, Proceedings, ICSE
    Pages433-436
    Number of pages4
    Publication statusPublished - 2002
    Event2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002 - Penang
    Duration: 19 Dec 200221 Dec 2002

    Other

    Other2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002
    CityPenang
    Period19/12/0221/12/02

    Fingerprint

    Computer hardware description languages
    Adders
    Computer aided design

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering
    • Electronic, Optical and Magnetic Materials

    Cite this

    Lakshmanan, N. V., Othman, M., & Mohamad, M. A. (2002). High performance parallel multiplier using Wallace-Booth algorithm. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE (pp. 433-436). [1217859]

    High performance parallel multiplier using Wallace-Booth algorithm. / Lakshmanan, [No Value]; Othman, Masuri; Mohamad, Mohamad Alauddin.

    IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2002. p. 433-436 1217859.

    Research output: Chapter in Book/Report/Conference proceedingConference contribution

    Lakshmanan, NV, Othman, M & Mohamad, MA 2002, High performance parallel multiplier using Wallace-Booth algorithm. in IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE., 1217859, pp. 433-436, 2002 5th IEEE International Conference on Semiconductor Electronics, ICSE 2002, Penang, 19/12/02.
    Lakshmanan NV, Othman M, Mohamad MA. High performance parallel multiplier using Wallace-Booth algorithm. In IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2002. p. 433-436. 1217859
    Lakshmanan, [No Value] ; Othman, Masuri ; Mohamad, Mohamad Alauddin. / High performance parallel multiplier using Wallace-Booth algorithm. IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE. 2002. pp. 433-436
    @inproceedings{46f87fb2ac2644aea65904b04b5ddfe1,
    title = "High performance parallel multiplier using Wallace-Booth algorithm",
    abstract = "This paper presents an efficient implementation of a VLSI high speed parallel multiplier using the Radix-4 modified Booth algorithm and the Wallace Tree structure .The design is structured for a n × m in multiplication where n can reach up to 126 bits. The Wallace Tree structure serves to compress the partial product term by a ratio of 3:2 [1] .To enhance the speed of operation, carry-look-ahead(CLA) adders are used which is independent on the number of bits of the two operands[2]. An efficient VHDL code was written and successfully simulated and synthesised using Altera's MaxplusII(10.0) and ModeISim3.4 CAD tools.",
    author = "Lakshmanan, {[No Value]} and Masuri Othman and Mohamad, {Mohamad Alauddin}",
    year = "2002",
    language = "English",
    isbn = "0780375785",
    pages = "433--436",
    booktitle = "IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE",

    }

    TY - GEN

    T1 - High performance parallel multiplier using Wallace-Booth algorithm

    AU - Lakshmanan, [No Value]

    AU - Othman, Masuri

    AU - Mohamad, Mohamad Alauddin

    PY - 2002

    Y1 - 2002

    N2 - This paper presents an efficient implementation of a VLSI high speed parallel multiplier using the Radix-4 modified Booth algorithm and the Wallace Tree structure .The design is structured for a n × m in multiplication where n can reach up to 126 bits. The Wallace Tree structure serves to compress the partial product term by a ratio of 3:2 [1] .To enhance the speed of operation, carry-look-ahead(CLA) adders are used which is independent on the number of bits of the two operands[2]. An efficient VHDL code was written and successfully simulated and synthesised using Altera's MaxplusII(10.0) and ModeISim3.4 CAD tools.

    AB - This paper presents an efficient implementation of a VLSI high speed parallel multiplier using the Radix-4 modified Booth algorithm and the Wallace Tree structure .The design is structured for a n × m in multiplication where n can reach up to 126 bits. The Wallace Tree structure serves to compress the partial product term by a ratio of 3:2 [1] .To enhance the speed of operation, carry-look-ahead(CLA) adders are used which is independent on the number of bits of the two operands[2]. An efficient VHDL code was written and successfully simulated and synthesised using Altera's MaxplusII(10.0) and ModeISim3.4 CAD tools.

    UR - http://www.scopus.com/inward/record.url?scp=35148845040&partnerID=8YFLogxK

    UR - http://www.scopus.com/inward/citedby.url?scp=35148845040&partnerID=8YFLogxK

    M3 - Conference contribution

    AN - SCOPUS:35148845040

    SN - 0780375785

    SN - 9780780375789

    SP - 433

    EP - 436

    BT - IEEE International Conference on Semiconductor Electronics, Proceedings, ICSE

    ER -