High performance CMOS charge pumps for phaselocked loop

Labonnah Farzana Rahman, Nurhazliza Bt Ariffin, Md. Mamun Ibne Reaz, Mohammad Marufuzzaman

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.

Original languageEnglish
Pages (from-to)241-249
Number of pages9
JournalTransactions on Electrical and Electronic Materials
Volume16
Issue number5
DOIs
Publication statusPublished - 1 Oct 2015

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Phase locked loops
Pumps
Transceivers
Data communication systems
Electric power utilization
Electric potential

Keywords

  • Charge pump (CP)
  • CMOS
  • Current mismatch
  • Phase-locked-loop (PLL)

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

High performance CMOS charge pumps for phaselocked loop. / Rahman, Labonnah Farzana; Bt Ariffin, Nurhazliza; Ibne Reaz, Md. Mamun; Marufuzzaman, Mohammad.

In: Transactions on Electrical and Electronic Materials, Vol. 16, No. 5, 01.10.2015, p. 241-249.

Research output: Contribution to journalArticle

Rahman, Labonnah Farzana ; Bt Ariffin, Nurhazliza ; Ibne Reaz, Md. Mamun ; Marufuzzaman, Mohammad. / High performance CMOS charge pumps for phaselocked loop. In: Transactions on Electrical and Electronic Materials. 2015 ; Vol. 16, No. 5. pp. 241-249.
@article{a3f484f82d3646c9be367dcbac49f904,
title = "High performance CMOS charge pumps for phaselocked loop",
abstract = "Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.",
keywords = "Charge pump (CP), CMOS, Current mismatch, Phase-locked-loop (PLL)",
author = "Rahman, {Labonnah Farzana} and {Bt Ariffin}, Nurhazliza and {Ibne Reaz}, {Md. Mamun} and Mohammad Marufuzzaman",
year = "2015",
month = "10",
day = "1",
doi = "10.4313/TEEM.2015.16.5.241",
language = "English",
volume = "16",
pages = "241--249",
journal = "Transactions on Electrical and Electronic Materials",
issn = "1229-7607",
publisher = "The Korean Institute of Electrical and Electronic Material Engineers",
number = "5",

}

TY - JOUR

T1 - High performance CMOS charge pumps for phaselocked loop

AU - Rahman, Labonnah Farzana

AU - Bt Ariffin, Nurhazliza

AU - Ibne Reaz, Md. Mamun

AU - Marufuzzaman, Mohammad

PY - 2015/10/1

Y1 - 2015/10/1

N2 - Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.

AB - Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.

KW - Charge pump (CP)

KW - CMOS

KW - Current mismatch

KW - Phase-locked-loop (PLL)

UR - http://www.scopus.com/inward/record.url?scp=84944743205&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84944743205&partnerID=8YFLogxK

U2 - 10.4313/TEEM.2015.16.5.241

DO - 10.4313/TEEM.2015.16.5.241

M3 - Article

AN - SCOPUS:84944743205

VL - 16

SP - 241

EP - 249

JO - Transactions on Electrical and Electronic Materials

JF - Transactions on Electrical and Electronic Materials

SN - 1229-7607

IS - 5

ER -