High degree of testability using full scan chain and ATPG-An industrial perspective

Md. Mamun Ibne Reaz, Weng F. Lee, Nor H. Hamid, Hai H. Lo, Ali Y M Shakaff

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

This study describes an efficient design methodology from an industrial perspective on utilizing Register Transfer Level (RTL) coding style, full scan chain implementation and Automatic Test Pattern Generation (ATPG) to achieve a high percentage of testability in the final Integrated Circuit (IC). The design methodology involves using an ASIC design flow with scan insertion and scan stitching performed after synthesis with scan flops set as don't_use during synthesis process. Based on this method of ASIC design flow with the RTL coding style and guideline, an in-house 64 bit processor core that executes 3 instructions per cycle, is implemented with 0.35 micron process technology with a single scan chain of 4600 flip-flops, achieving an ATPG pattern for stuck-at at 100% test coverage and 99.81% fault coverage. Thus, creating high testability coverage with the ATPG pattern can be achieved by having a fully synchronous design using the proposed RTL coding style and full scan chain implementation. This study also describes the work around methods used when dealing with cost reduction involving reduction of test pin on the IC chip package.

Original languageEnglish
Pages (from-to)2613-2618
Number of pages6
JournalJournal of Applied Sciences
Volume9
Issue number14
DOIs
Publication statusPublished - 2009

Fingerprint

Automatic test pattern generation
Application specific integrated circuits
Integrated circuits
Flip flop circuits
Cost reduction

Keywords

  • Automatic test pattern generation
  • Design for test
  • DFT design methodology
  • Guideline
  • IC chip packaging
  • Integrated circuit
  • Register transfer level
  • Scan chain
  • Sharing pin for testing
  • VLSI

ASJC Scopus subject areas

  • General

Cite this

High degree of testability using full scan chain and ATPG-An industrial perspective. / Ibne Reaz, Md. Mamun; Lee, Weng F.; Hamid, Nor H.; Lo, Hai H.; Shakaff, Ali Y M.

In: Journal of Applied Sciences, Vol. 9, No. 14, 2009, p. 2613-2618.

Research output: Contribution to journalArticle

Ibne Reaz, Md. Mamun ; Lee, Weng F. ; Hamid, Nor H. ; Lo, Hai H. ; Shakaff, Ali Y M. / High degree of testability using full scan chain and ATPG-An industrial perspective. In: Journal of Applied Sciences. 2009 ; Vol. 9, No. 14. pp. 2613-2618.
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