Hardware realization of an efficient fetal QRS complex detection algorithm

M. I. Ibrahimy, Md. Mamun Ibne Reaz, M. A Mohd Ali, T. H. Khoon, A. F. Ismail

Research output: Contribution to journalArticle

9 Citations (Scopus)

Abstract

An algorithm has been developed for the simultaneous measurement of the fetal and maternal heart rates from the maternal abdominal electrocardiogram during pregnancy and labor for fetal monitoring. The algorithm is based on cross-correlation, adaptive thresholding and statistical properties in the time domain. The algorithm was initially developed and simulated in Visual C++. Once the functionality is verified, it is then converted in VHDL - hardware description language for FPGA implementation. The design is synthesized and fitted into Altera's Stratix EP1S10 using the Quartus II platform because of its enhanced DSP capability. Test case results showed an error percentage of around ±0.3% and ±0.5% for the detection of maternal and fetal heart rate respectively. The system is capable to run at a maximum clock frequency of 48.56MHz, and consumed 9633 logic elements, 101616 memory space and 4 units of DSP blocks.

Original languageEnglish
Pages (from-to)575-581
Number of pages7
JournalWSEAS Transactions on Circuits and Systems
Volume5
Issue number4
Publication statusPublished - Apr 2006
Externally publishedYes

Fingerprint

Computer hardware description languages
Hardware
Fetal monitoring
Electrocardiography
Field programmable gate arrays (FPGA)
Clocks
Personnel
Data storage equipment

Keywords

  • Electrocardiogram
  • Fetal heart rate
  • FPGA
  • VHDL

ASJC Scopus subject areas

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Hardware realization of an efficient fetal QRS complex detection algorithm. / Ibrahimy, M. I.; Ibne Reaz, Md. Mamun; Ali, M. A Mohd; Khoon, T. H.; Ismail, A. F.

In: WSEAS Transactions on Circuits and Systems, Vol. 5, No. 4, 04.2006, p. 575-581.

Research output: Contribution to journalArticle

Ibrahimy, M. I. ; Ibne Reaz, Md. Mamun ; Ali, M. A Mohd ; Khoon, T. H. ; Ismail, A. F. / Hardware realization of an efficient fetal QRS complex detection algorithm. In: WSEAS Transactions on Circuits and Systems. 2006 ; Vol. 5, No. 4. pp. 575-581.
@article{804f2fa2863c455492454ea41135abda,
title = "Hardware realization of an efficient fetal QRS complex detection algorithm",
abstract = "An algorithm has been developed for the simultaneous measurement of the fetal and maternal heart rates from the maternal abdominal electrocardiogram during pregnancy and labor for fetal monitoring. The algorithm is based on cross-correlation, adaptive thresholding and statistical properties in the time domain. The algorithm was initially developed and simulated in Visual C++. Once the functionality is verified, it is then converted in VHDL - hardware description language for FPGA implementation. The design is synthesized and fitted into Altera's Stratix EP1S10 using the Quartus II platform because of its enhanced DSP capability. Test case results showed an error percentage of around ±0.3{\%} and ±0.5{\%} for the detection of maternal and fetal heart rate respectively. The system is capable to run at a maximum clock frequency of 48.56MHz, and consumed 9633 logic elements, 101616 memory space and 4 units of DSP blocks.",
keywords = "Electrocardiogram, Fetal heart rate, FPGA, VHDL",
author = "Ibrahimy, {M. I.} and {Ibne Reaz}, {Md. Mamun} and Ali, {M. A Mohd} and Khoon, {T. H.} and Ismail, {A. F.}",
year = "2006",
month = "4",
language = "English",
volume = "5",
pages = "575--581",
journal = "WSEAS Transactions on Circuits and Systems",
issn = "1109-2734",
publisher = "World Scientific and Engineering Academy and Society",
number = "4",

}

TY - JOUR

T1 - Hardware realization of an efficient fetal QRS complex detection algorithm

AU - Ibrahimy, M. I.

AU - Ibne Reaz, Md. Mamun

AU - Ali, M. A Mohd

AU - Khoon, T. H.

AU - Ismail, A. F.

PY - 2006/4

Y1 - 2006/4

N2 - An algorithm has been developed for the simultaneous measurement of the fetal and maternal heart rates from the maternal abdominal electrocardiogram during pregnancy and labor for fetal monitoring. The algorithm is based on cross-correlation, adaptive thresholding and statistical properties in the time domain. The algorithm was initially developed and simulated in Visual C++. Once the functionality is verified, it is then converted in VHDL - hardware description language for FPGA implementation. The design is synthesized and fitted into Altera's Stratix EP1S10 using the Quartus II platform because of its enhanced DSP capability. Test case results showed an error percentage of around ±0.3% and ±0.5% for the detection of maternal and fetal heart rate respectively. The system is capable to run at a maximum clock frequency of 48.56MHz, and consumed 9633 logic elements, 101616 memory space and 4 units of DSP blocks.

AB - An algorithm has been developed for the simultaneous measurement of the fetal and maternal heart rates from the maternal abdominal electrocardiogram during pregnancy and labor for fetal monitoring. The algorithm is based on cross-correlation, adaptive thresholding and statistical properties in the time domain. The algorithm was initially developed and simulated in Visual C++. Once the functionality is verified, it is then converted in VHDL - hardware description language for FPGA implementation. The design is synthesized and fitted into Altera's Stratix EP1S10 using the Quartus II platform because of its enhanced DSP capability. Test case results showed an error percentage of around ±0.3% and ±0.5% for the detection of maternal and fetal heart rate respectively. The system is capable to run at a maximum clock frequency of 48.56MHz, and consumed 9633 logic elements, 101616 memory space and 4 units of DSP blocks.

KW - Electrocardiogram

KW - Fetal heart rate

KW - FPGA

KW - VHDL

UR - http://www.scopus.com/inward/record.url?scp=33744522404&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=33744522404&partnerID=8YFLogxK

M3 - Article

VL - 5

SP - 575

EP - 581

JO - WSEAS Transactions on Circuits and Systems

JF - WSEAS Transactions on Circuits and Systems

SN - 1109-2734

IS - 4

ER -