Hardware prototyping of root raised cosine FIR filter for 2x2 MIMO channel sounder

M. Habib Ullah, Mandeep Singh Jit Singh, Sumazly Sulaiman, M. Shamim Shumon, Mohammad Tariqul Islam

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A root raised cosine (RRC) finite impulse response (FIR) digital filter using Xilinx system generator blockset in simulink environment is presented in this paper. The RRC filter is designed and implemented as a part of BPSK transmitter for CDM based 2x2 MIMO channel sounder. The role of the filter in the transmitter is pulse shaping. Pulse shaping is needed to specify the bandwidth of band limited base band communication system. In this paper, a 32 order square root FIR digital filter is designed and implemented in Xilinx FPGA.

Original languageEnglish
Pages (from-to)375-382
Number of pages8
JournalAustralian Journal of Basic and Applied Sciences
Volume5
Issue number11
Publication statusPublished - Nov 2011

Fingerprint

Pulse shaping
FIR filters
Digital filters
MIMO systems
Transmitters
Acoustic waves
Hardware
Field programmable gate arrays (FPGA)
Communication systems
Bandwidth

Keywords

  • MIMO Channel Sounder
  • Pulse Shaping
  • Root Raised Cosine Filter
  • Xilinx FPGA

ASJC Scopus subject areas

  • General

Cite this

Hardware prototyping of root raised cosine FIR filter for 2x2 MIMO channel sounder. / Habib Ullah, M.; Jit Singh, Mandeep Singh; Sulaiman, Sumazly; Shamim Shumon, M.; Islam, Mohammad Tariqul.

In: Australian Journal of Basic and Applied Sciences, Vol. 5, No. 11, 11.2011, p. 375-382.

Research output: Contribution to journalArticle

@article{3a24e44e25ae41179ac721dd26fb9e02,
title = "Hardware prototyping of root raised cosine FIR filter for 2x2 MIMO channel sounder",
abstract = "A root raised cosine (RRC) finite impulse response (FIR) digital filter using Xilinx system generator blockset in simulink environment is presented in this paper. The RRC filter is designed and implemented as a part of BPSK transmitter for CDM based 2x2 MIMO channel sounder. The role of the filter in the transmitter is pulse shaping. Pulse shaping is needed to specify the bandwidth of band limited base band communication system. In this paper, a 32 order square root FIR digital filter is designed and implemented in Xilinx FPGA.",
keywords = "MIMO Channel Sounder, Pulse Shaping, Root Raised Cosine Filter, Xilinx FPGA",
author = "{Habib Ullah}, M. and {Jit Singh}, {Mandeep Singh} and Sumazly Sulaiman and {Shamim Shumon}, M. and Islam, {Mohammad Tariqul}",
year = "2011",
month = "11",
language = "English",
volume = "5",
pages = "375--382",
journal = "Australian Journal of Basic and Applied Sciences",
issn = "1991-8178",
publisher = "INSInet Publications",
number = "11",

}

TY - JOUR

T1 - Hardware prototyping of root raised cosine FIR filter for 2x2 MIMO channel sounder

AU - Habib Ullah, M.

AU - Jit Singh, Mandeep Singh

AU - Sulaiman, Sumazly

AU - Shamim Shumon, M.

AU - Islam, Mohammad Tariqul

PY - 2011/11

Y1 - 2011/11

N2 - A root raised cosine (RRC) finite impulse response (FIR) digital filter using Xilinx system generator blockset in simulink environment is presented in this paper. The RRC filter is designed and implemented as a part of BPSK transmitter for CDM based 2x2 MIMO channel sounder. The role of the filter in the transmitter is pulse shaping. Pulse shaping is needed to specify the bandwidth of band limited base band communication system. In this paper, a 32 order square root FIR digital filter is designed and implemented in Xilinx FPGA.

AB - A root raised cosine (RRC) finite impulse response (FIR) digital filter using Xilinx system generator blockset in simulink environment is presented in this paper. The RRC filter is designed and implemented as a part of BPSK transmitter for CDM based 2x2 MIMO channel sounder. The role of the filter in the transmitter is pulse shaping. Pulse shaping is needed to specify the bandwidth of band limited base band communication system. In this paper, a 32 order square root FIR digital filter is designed and implemented in Xilinx FPGA.

KW - MIMO Channel Sounder

KW - Pulse Shaping

KW - Root Raised Cosine Filter

KW - Xilinx FPGA

UR - http://www.scopus.com/inward/record.url?scp=84255172832&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84255172832&partnerID=8YFLogxK

M3 - Article

AN - SCOPUS:84255172832

VL - 5

SP - 375

EP - 382

JO - Australian Journal of Basic and Applied Sciences

JF - Australian Journal of Basic and Applied Sciences

SN - 1991-8178

IS - 11

ER -