Hardware prototyping of neural network based fetal electrocardiogram extraction

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

The aim of this paper is to model the algorithm for Fetal ECG (FECG) extraction from composite abdominal ECG (AECG) using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation. Artificial Neural Network that provides efficient and effective ways of separating FECG signal from composite AECG signal has been designed. The proposed method gives an accuracy of 93.7% for R-peak detection in FHR monitoring. The designed VHDL model is synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 8.0 Web Edition for FPGA implementation.

Original languageEnglish
Pages (from-to)52-55
Number of pages4
JournalMeasurement Science Review
Volume12
Issue number2
DOIs
Publication statusPublished - 1 Jan 2012

Fingerprint

electrocardiography
hardware description languages
Electrocardiography
Computer hardware description languages
hardware
field-programmable gate arrays
Neural networks
Hardware
VHSIC (circuits)
Field programmable gate arrays (FPGA)
composite materials
Composite materials
Integrated circuits
Monitoring

Keywords

  • Fetal electrocardiogram
  • FPGA
  • Neural network
  • VHDL

ASJC Scopus subject areas

  • Instrumentation
  • Biomedical Engineering
  • Control and Systems Engineering

Cite this

Hardware prototyping of neural network based fetal electrocardiogram extraction. / Hasan, M.; Ibne Reaz, Md. Mamun.

In: Measurement Science Review, Vol. 12, No. 2, 01.01.2012, p. 52-55.

Research output: Contribution to journalArticle

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