Hardware implementation of higher data rate anti-collision algorithm of RFID systems

Jahariah Sampe, Masuri Othman, Mahamod Ismail

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

This paper presents a proposed hardware implementation of higher data rate Fast Detection Anti-collision Algorithm (higher data rate FDACA) for Radio Frequency Identification (RFID) systems. The proposed higher data rate FDACA is deterministic anti-collision technique and is based on Time Division Multiplexing (TDM). The primary FDACA is novel in terms of a faster identification by reducing the number of iterations during the identification process. The primary FDACA also reads the identification (ID) bits at once regardless of its length. It also does not require the tags to remember the instructions from the reader during the communication process. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim XE II and synthesized using Xilinx synthesis technology (XST). The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) board model Virtex II Xc2v250. The output waveforms from the FPGA have been displayed on Tektronix Logic Analyzer model TLA 5201 for real time verification. From the results, its show that the proposed higher data rate FDACA system enables to identify the tags without error until the maximum operating frequency of 160MHz. Therefore the maximum data rate of this hardware implemented anti-collision algorithm is 640 Mbps for eight bit ID length and four input/output lines.

Original languageEnglish
Pages (from-to)561-567
Number of pages7
JournalEuropean Journal of Scientific Research
Volume18
Issue number3
Publication statusPublished - 2007

Fingerprint

Radio Frequency Identification Device
radio frequency identification
Hardware Implementation
Radio Frequency Identification
Radio frequency identification (RFID)
hardware
Collision
collision
radio
Hardware
Computer hardware description languages
Time division multiplexing
Technology
synthesis
Grid
Output
Multiplexing
Waveform
Communication
Division

Keywords

  • Deterministic anti-collision
  • Faster identification time
  • Real time verification
  • Time division multiplexing

ASJC Scopus subject areas

  • General

Cite this

Hardware implementation of higher data rate anti-collision algorithm of RFID systems. / Sampe, Jahariah; Othman, Masuri; Ismail, Mahamod.

In: European Journal of Scientific Research, Vol. 18, No. 3, 2007, p. 561-567.

Research output: Contribution to journalArticle

@article{1dc7437113054390adb212b90b97a2cf,
title = "Hardware implementation of higher data rate anti-collision algorithm of RFID systems",
abstract = "This paper presents a proposed hardware implementation of higher data rate Fast Detection Anti-collision Algorithm (higher data rate FDACA) for Radio Frequency Identification (RFID) systems. The proposed higher data rate FDACA is deterministic anti-collision technique and is based on Time Division Multiplexing (TDM). The primary FDACA is novel in terms of a faster identification by reducing the number of iterations during the identification process. The primary FDACA also reads the identification (ID) bits at once regardless of its length. It also does not require the tags to remember the instructions from the reader during the communication process. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim XE II and synthesized using Xilinx synthesis technology (XST). The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) board model Virtex II Xc2v250. The output waveforms from the FPGA have been displayed on Tektronix Logic Analyzer model TLA 5201 for real time verification. From the results, its show that the proposed higher data rate FDACA system enables to identify the tags without error until the maximum operating frequency of 160MHz. Therefore the maximum data rate of this hardware implemented anti-collision algorithm is 640 Mbps for eight bit ID length and four input/output lines.",
keywords = "Deterministic anti-collision, Faster identification time, Real time verification, Time division multiplexing",
author = "Jahariah Sampe and Masuri Othman and Mahamod Ismail",
year = "2007",
language = "English",
volume = "18",
pages = "561--567",
journal = "European Journal of Scientific Research",
issn = "1450-202X",
publisher = "European Journals Inc.",
number = "3",

}

TY - JOUR

T1 - Hardware implementation of higher data rate anti-collision algorithm of RFID systems

AU - Sampe, Jahariah

AU - Othman, Masuri

AU - Ismail, Mahamod

PY - 2007

Y1 - 2007

N2 - This paper presents a proposed hardware implementation of higher data rate Fast Detection Anti-collision Algorithm (higher data rate FDACA) for Radio Frequency Identification (RFID) systems. The proposed higher data rate FDACA is deterministic anti-collision technique and is based on Time Division Multiplexing (TDM). The primary FDACA is novel in terms of a faster identification by reducing the number of iterations during the identification process. The primary FDACA also reads the identification (ID) bits at once regardless of its length. It also does not require the tags to remember the instructions from the reader during the communication process. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim XE II and synthesized using Xilinx synthesis technology (XST). The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) board model Virtex II Xc2v250. The output waveforms from the FPGA have been displayed on Tektronix Logic Analyzer model TLA 5201 for real time verification. From the results, its show that the proposed higher data rate FDACA system enables to identify the tags without error until the maximum operating frequency of 160MHz. Therefore the maximum data rate of this hardware implemented anti-collision algorithm is 640 Mbps for eight bit ID length and four input/output lines.

AB - This paper presents a proposed hardware implementation of higher data rate Fast Detection Anti-collision Algorithm (higher data rate FDACA) for Radio Frequency Identification (RFID) systems. The proposed higher data rate FDACA is deterministic anti-collision technique and is based on Time Division Multiplexing (TDM). The primary FDACA is novel in terms of a faster identification by reducing the number of iterations during the identification process. The primary FDACA also reads the identification (ID) bits at once regardless of its length. It also does not require the tags to remember the instructions from the reader during the communication process. The proposed system is designed using Verilog HDL. The system is simulated using Modelsim XE II and synthesized using Xilinx synthesis technology (XST). The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) board model Virtex II Xc2v250. The output waveforms from the FPGA have been displayed on Tektronix Logic Analyzer model TLA 5201 for real time verification. From the results, its show that the proposed higher data rate FDACA system enables to identify the tags without error until the maximum operating frequency of 160MHz. Therefore the maximum data rate of this hardware implemented anti-collision algorithm is 640 Mbps for eight bit ID length and four input/output lines.

KW - Deterministic anti-collision

KW - Faster identification time

KW - Real time verification

KW - Time division multiplexing

UR - http://www.scopus.com/inward/record.url?scp=37349088156&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=37349088156&partnerID=8YFLogxK

M3 - Article

VL - 18

SP - 561

EP - 567

JO - European Journal of Scientific Research

JF - European Journal of Scientific Research

SN - 1450-202X

IS - 3

ER -