Hardware implementation of 32-bit high-speed direct digital frequency synthesizer

Salah Hasan Ibrahim, Sawal Hamid Md Ali, Md. Shabiul Islam

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

The design and implementation of a high-speed direct digital frequency synthesizer are presented. A modified Brent-Kung parallel adder is combined with pipelining technique to improve the speed of the system. A gated clock technique is proposed to reduce the number of registers in the phase accumulator design. The quarter wave symmetry technique is used to store only one quarter of the sine wave. The ROM lookup table (LUT) is partitioned into three 4-bit sub-ROMs based on angular decomposition technique and trigonometric identity. Exploiting the advantages of sine-cosine symmetrical attributes together with XOR logic gates, one sub-ROM block can be removed from the design. These techniques, compressed the ROM into 368 bits. The ROM compressed ratio is 534.2: 1, with only two adders, two multipliers, and XOR-gates with high frequency resolution of 0.029 Hz. These techniques make the direct digital frequency synthesizer an attractive candidate for wireless communication applications.

Original languageEnglish
Article number131568
JournalScientific World Journal
Volume2014
DOIs
Publication statusPublished - 2014

Fingerprint

Frequency synthesizers
ROM
hardware
Hardware
Adders
symmetry
Table lookup
communication
decomposition
Logic gates
Clocks
speed
Decomposition
Communication

ASJC Scopus subject areas

  • Biochemistry, Genetics and Molecular Biology(all)
  • Environmental Science(all)
  • Medicine(all)

Cite this

Hardware implementation of 32-bit high-speed direct digital frequency synthesizer. / Ibrahim, Salah Hasan; Md Ali, Sawal Hamid; Islam, Md. Shabiul.

In: Scientific World Journal, Vol. 2014, 131568, 2014.

Research output: Contribution to journalArticle

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